From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joakim Tjernlund <joakim.tjernlund@transmode.se>
Date: Thu, 5 Nov 2015 08:03:53 +0000
Subject: [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for
 DDR4 for LSCH3
In-Reply-To: <1446660203-18047-1-git-send-email-yorksun@freescale.com>
References: <1446660203-18047-1-git-send-email-yorksun@freescale.com>
Message-ID: <1446710633.21216.119.camel@transmode.se>
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To: u-boot@lists.denx.de

On Wed, 2015-11-04 at 10:03 -0800, York Sun wrote:
> This patch set revises the DDR driver to support higher speed for DDR4
> under heavy load (two dual-rank DIMMs) for four-chipselect interleaving.
> Single quad-rank DIMM is not supported yet.

Hi York

Seeing these patches reminds me about something I have been mening to ask,
Is it possible init the ddr controller/ddr ram (using ECC also) but
still retain (parts of) memory contents?

I am looking at keeping data at the end of memory when performing a
warm start, but still init the controll/ddr ram (without D_INIT set).
This way one could pick up any changes to DDR timing if needed.
Before reboot, ddr ram is set to Self Refresh(SR).

 Jocke