[U-Boot] [PATCH 08/10] x86: Convert to use driver model timer

Bin Meng
2015-11-05T14:02:49Z

Convert all x86 boards to use driver model tsc timer.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

arch/x86/cpu/baytrail/valleyview.c | 3 ---
arch/x86/cpu/coreboot/timestamp.c | 22 ----------------------
arch/x86/cpu/efi/efi.c | 4 ----
arch/x86/cpu/ivybridge/cpu.c | 1 -
arch/x86/cpu/qemu/qemu.c | 3 ---
arch/x86/cpu/quark/quark.c | 3 ---
arch/x86/cpu/queensbay/tnc.c | 3 ---
arch/x86/dts/bayleybay.dts | 1 +
arch/x86/dts/broadwell_som-6896.dts | 1 +
arch/x86/dts/chromebook_link.dts | 1 +
arch/x86/dts/chromebox_panther.dts | 1 +
arch/x86/dts/crownbay.dts | 1 +
arch/x86/dts/efi.dts | 5 +++++
arch/x86/dts/galileo.dts | 5 +++++
arch/x86/dts/minnowmax.dts | 1 +
arch/x86/dts/qemu-x86_i440fx.dts | 5 +++++
arch/x86/dts/qemu-x86_q35.dts | 5 +++++
arch/x86/dts/tsc_timer.dtsi | 7 +++++++
configs/bayleybay_defconfig | 1 +
configs/chromebook_link_defconfig | 2 +-
configs/chromebox_panther_defconfig | 2 +-
configs/coreboot-x86_defconfig | 2 +-
configs/crownbay_defconfig | 1 +
configs/efi-x86_defconfig | 1 +
configs/galileo_defconfig | 1 +
configs/minnowmax_defconfig | 1 +
configs/qemu-x86_defconfig | 1 +
27 files changed, 42 insertions(+), 42 deletions(-)
create mode 100644 arch/x86/dts/tsc_timer.dtsi

diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c
index a009c14..9b30451 100644
--- a/arch/x86/cpu/baytrail/valleyview.c
+++ b/arch/x86/cpu/baytrail/valleyview.c
@@ -28,9 +28,6 @@ int arch_cpu_init(void)
int ret;

post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif

ret = x86_cpu_init_f();
if (ret)
diff --git a/arch/x86/cpu/coreboot/timestamp.c b/arch/x86/cpu/coreboot/timestamp.c
index 0edee6b..b382795 100644
--- a/arch/x86/cpu/coreboot/timestamp.c
+++ b/arch/x86/cpu/coreboot/timestamp.c
@@ -27,28 +27,6 @@ static struct timestamp_table *ts_table __attribute__((section(".data")));

void timestamp_init(void)
{
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- uint64_t base_time;
-#endif
-
- ts_table = lib_sysinfo.tstamp_table;
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- /*
- * If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
- * of base_time in coreboot's timestamp table as our timer base,
- * otherwise TSC counter value will be used.
- *
- * Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
- * the value of base_time in the timestamp table is still zero, so
- * we must exclude this case too (this is currently seen on booting
- * coreboot in qemu)
- */
- if (ts_table && ts_table->base_time)
- base_time = ts_table->base_time;
- else
- base_time = rdtsc();
- timer_set_base(base_time);
-#endif
timestamp_add_now(TS_U_BOOT_INITTED);
}

diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c
index 75ba0d4..993ab8d 100644
--- a/arch/x86/cpu/efi/efi.c
+++ b/arch/x86/cpu/efi/efi.c
@@ -10,10 +10,6 @@

int arch_cpu_init(void)
{
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif
-
return 0;
}

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index 0e6512c..0387444 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -118,7 +118,6 @@ static void set_spi_speed(void)
int arch_cpu_init(void)
{
post_code(POST_CPU_INIT);
- timer_set_base(rdtsc());

return x86_cpu_init_f();
}
diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c
index 7c03e02..13e83a1 100644
--- a/arch/x86/cpu/qemu/qemu.c
+++ b/arch/x86/cpu/qemu/qemu.c
@@ -14,9 +14,6 @@ int arch_cpu_init(void)
int ret;

post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif

ret = x86_cpu_init_f();
if (ret)
diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c
index f737e19..c2bf497 100644
--- a/arch/x86/cpu/quark/quark.c
+++ b/arch/x86/cpu/quark/quark.c
@@ -233,9 +233,6 @@ int arch_cpu_init(void)
int ret;

post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif

ret = x86_cpu_init_f();
if (ret)
diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 933d189..fb81919 100644
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -52,9 +52,6 @@ int arch_cpu_init(void)
int ret;

post_code(POST_CPU_INIT);
-#ifdef CONFIG_SYS_X86_TSC_TIMER
- timer_set_base(rdtsc());
-#endif

ret = x86_cpu_init_f();
if (ret)
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts
index 52d0999..f8901c3 100644
--- a/arch/x86/dts/bayleybay.dts
+++ b/arch/x86/dts/bayleybay.dts
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Intel Bayley Bay";
diff --git a/arch/x86/dts/broadwell_som-6896.dts b/arch/x86/dts/broadwell_som-6896.dts
index a6b5d0f..194f0eb 100644
--- a/arch/x86/dts/broadwell_som-6896.dts
+++ b/arch/x86/dts/broadwell_som-6896.dts
@@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Advantech SOM-6896";
diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index f27263a..d3e0758 100644
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Google Link";
diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 61e8f2f..4e2b517 100644
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -3,6 +3,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Google Panther";
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts
index 3e354c4..c0a640d 100644
--- a/arch/x86/dts/crownbay.dts
+++ b/arch/x86/dts/crownbay.dts
@@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Intel Crown Bay";
diff --git a/arch/x86/dts/efi.dts b/arch/x86/dts/efi.dts
index 1f50428..68b42e7 100644
--- a/arch/x86/dts/efi.dts
+++ b/arch/x86/dts/efi.dts
@@ -7,6 +7,7 @@
/dts-v1/;

/include/ "skeleton.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "EFI";
@@ -16,6 +17,10 @@
stdout-path = &serial;
};

+ tsc-timer {
+ clock-frequency = <100000000>;
+ };
+
serial: serial {
compatible = "efi,uart";
};
diff --git a/arch/x86/dts/galileo.dts b/arch/x86/dts/galileo.dts
index b49b1f5..2342de7 100644
--- a/arch/x86/dts/galileo.dts
+++ b/arch/x86/dts/galileo.dts
@@ -11,6 +11,7 @@

/include/ "skeleton.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Intel Galileo";
@@ -28,6 +29,10 @@
stdout-path = &pciuart0;
};

+ tsc-timer {
+ clock-frequency = <400000000>;
+ };
+
mrc {
compatible = "intel,quark-mrc";
flags = <MRC_FLAG_SCRAMBLE_EN>;
diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index b03f987..bbfd6d4 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -12,6 +12,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "Intel Minnowboard Max";
diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts
index fc74cd0..4861b09 100644
--- a/arch/x86/dts/qemu-x86_i440fx.dts
+++ b/arch/x86/dts/qemu-x86_i440fx.dts
@@ -11,6 +11,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "QEMU x86 (I440FX)";
@@ -43,6 +44,10 @@
};
};

+ tsc-timer {
+ clock-frequency = <100000000>;
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts
index 7f16971..ff293fe 100644
--- a/arch/x86/dts/qemu-x86_q35.dts
+++ b/arch/x86/dts/qemu-x86_q35.dts
@@ -21,6 +21,7 @@
/include/ "skeleton.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
+/include/ "tsc_timer.dtsi"

/ {
model = "QEMU x86 (Q35)";
@@ -54,6 +55,10 @@
};
};

+ tsc-timer {
+ clock-frequency = <100000000>;
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
diff --git a/arch/x86/dts/tsc_timer.dtsi b/arch/x86/dts/tsc_timer.dtsi
new file mode 100644
index 0000000..d1cc31e
--- /dev/null
+++ b/arch/x86/dts/tsc_timer.dtsi
@@ -0,0 +1,7 @@
+/ {
+ tsc-timer {
+ compatible = "x86,tsc-timer";
+ u-boot,dm-pre-reloc;
+ counter-64bit;
+ };
+};
diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig
index fc40da8..e9abbd0 100644
--- a/configs/bayleybay_defconfig
+++ b/configs/bayleybay_defconfig
@@ -24,6 +24,7 @@ CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
diff --git a/configs/chromebook_link_defconfig b/configs/chromebook_link_defconfig
index 78a9470..c280478 100644
--- a/configs/chromebook_link_defconfig
+++ b/configs/chromebook_link_defconfig
@@ -26,7 +26,7 @@ CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
CONFIG_DEBUG_UART_BOARD_INIT=y
-CONFIG_DM_TPM=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig
index 663aab0..fca6e53 100644
--- a/configs/chromebox_panther_defconfig
+++ b/configs/chromebox_panther_defconfig
@@ -21,7 +21,7 @@ CONFIG_CROS_EC_LPC=y
CONFIG_SPI_FLASH=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DM_TPM=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
diff --git a/configs/coreboot-x86_defconfig b/configs/coreboot-x86_defconfig
index 438e43b..3f2cff8 100644
--- a/configs/coreboot-x86_defconfig
+++ b/configs/coreboot-x86_defconfig
@@ -17,7 +17,7 @@ CONFIG_DM_ETH=y
CONFIG_E1000=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
-CONFIG_DM_TPM=y
+CONFIG_TIMER=y
CONFIG_TPM_TIS_LPC=y
CONFIG_USB=y
CONFIG_DM_USB=y
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig
index d036c05..7ae36b6 100644
--- a/configs/crownbay_defconfig
+++ b/configs/crownbay_defconfig
@@ -23,6 +23,7 @@ CONFIG_E1000=y
CONFIG_PCH_GBE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
diff --git a/configs/efi-x86_defconfig b/configs/efi-x86_defconfig
index 43fb0c4..fd90739 100644
--- a/configs/efi-x86_defconfig
+++ b/configs/efi-x86_defconfig
@@ -13,4 +13,5 @@ CONFIG_DEBUG_EFI_CONSOLE=y
CONFIG_DEBUG_UART_BASE=0
CONFIG_DEBUG_UART_CLOCK=0
# CONFIG_X86_SERIAL is not set
+CONFIG_TIMER=y
CONFIG_EFI=y
diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig
index 1e1ce95..6421e5b 100644
--- a/configs/galileo_defconfig
+++ b/configs/galileo_defconfig
@@ -18,6 +18,7 @@ CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_DM_PCI=y
CONFIG_DM_RTC=y
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig
index 8f99f0e..ef3b816 100644
--- a/configs/minnowmax_defconfig
+++ b/configs/minnowmax_defconfig
@@ -25,6 +25,7 @@ CONFIG_DM_RTC=y
CONFIG_DEBUG_UART=y
CONFIG_DEBUG_UART_BASE=0x3f8
CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_VIDEO_VESA=y
diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig
index f4cc862..2835e03 100644
--- a/configs/qemu-x86_defconfig
+++ b/configs/qemu-x86_defconfig
@@ -18,6 +18,7 @@ CONFIG_SPI_FLASH=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_DM_RTC=y
+CONFIG_TIMER=y
CONFIG_VIDEO_VESA=y
CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
CONFIG_FRAMEBUFFER_VESA_MODE_111=y
--
1.8.2.1