[U-Boot] [PATCH] Revert "net: phy: delay only if reset handler is registered"

["Jörg Krause" <joerg.krause@embedded.rocks>]

Hi Fabio,

On Di, 2015-11-17 at 14:25 -0200, Fabio Estevam wrote:
> This reverts commit 59370f3fcd135089c402c93720a87c688abe600c.
> 
> This commit breaks ethernet on at least mx6 Riotboard and
> mx6sxsabresd boards.
> 
> Reported-by: Catalin Crenguta <catalin.crenguta@gmail.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> ?drivers/net/phy/phy.c | 8 +++-----
> ?1 file changed, 3 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index d7364ff..9e68f1d 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -771,13 +771,11 @@ struct phy_device *phy_find_by_mask(struct
> mii_dev *bus, unsigned phy_mask,
> ?		phy_interface_t interface)
> ?{
> ?	/* Reset the bus */
> -	if (bus->reset) {
> +	if (bus->reset)
> ?		bus->reset(bus);
> ?
> -		/* Wait 15ms to make sure the PHY has come out of
> hard reset */
> -		udelay(15000);
> -	}
> -
> +	/* Wait 15ms to make sure the PHY has come out of hard reset
> */
> +	udelay(15000);
> ?	return get_phy_device_by_mask(bus, phy_mask, interface);
> ?}
> ?

I think this is not the right thing to do here. It is true that the
AR8035 ethernet chip of the RioTboard needs the clock to be stable for
at least 1ms before RESET can be deasserted. This why it fails, if
there is no MII reset function defined.

I think the right place to handle reset delays is the?board_eth_init().
The value of 15ms currently used looks to me like an arbitrary value. I
am not sure where this value is comming from. Some chips need more,
some less time to delay after a reset.

This is snippet of how I do it for a custom i.MX28-EVK-based board:

int board_eth_init(bd_t *bis) {
??cpu_eth_init(bis);
??/* Power-on FEC */
? gpio_direction_output(MX28_PAD_LCD_D21__GPIO_1_21, 0);
??/* Reset FEC PHY */
??gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
??/* Deassert nRST after 25 ms from power-up on (= t_purstd) */
??udelay(25000);
??gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
??fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
}

Best regards
J?rg Krause