[U-Boot] [PATCH 03/10] ARM: socfpga: arria10: add reset manager for Arria10

[dinguyen at opensource.altera.com <dinguyen@opensource.altera.com>]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the defines for the reset manager and some basic reset functionality.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/arria10/reset_manager_a10.c  |  83 +++++++++++
 .../mach-socfpga/include/mach/reset_manager_a10.h  | 162 +++++++++++++++++++++
 2 files changed, 245 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/arria10/reset_manager_a10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_a10.h

diff --git a/arch/arm/mach-socfpga/arria10/reset_manager_a10.c b/arch/arm/mach-socfpga/arria10/reset_manager_a10.c
new file mode 100644
index 0000000..e2d315a
--- /dev/null
+++ b/arch/arm/mach-socfpga/arria10/reset_manager_a10.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/reset_manager_a10.h>
+#include <asm/arch/system_manager_a10.h>
+#include <fdtdec.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_reset_manager *reset_manager_base =
+		(void *)SOCFPGA_RSTMGR_ADDRESS;
+
+/*
+ * Assert or de-assert SoCFPGA reset manager reset.
+ */
+void socfpga_per_reset(u32 reset, int set)
+{
+	const void *reg;
+
+	if (RSTMGR_BANK(reset) == 0)
+		reg = &reset_manager_base->mpu_mod_rst;
+	else if (RSTMGR_BANK(reset) == 1)
+		reg = &reset_manager_base->per0_mod_rst;
+	else if (RSTMGR_BANK(reset) == 2)
+		reg = &reset_manager_base->per1_mod_rst;
+	else if (RSTMGR_BANK(reset) == 3)
+		reg = &reset_manager_base->brg_mod_rst;
+	else if (RSTMGR_BANK(reset) == 4)
+		reg = &reset_manager_base->sys_mod_rst;
+	else    /* Invalid reset register, do nothing */
+		return;
+
+	if (set)
+		setbits_le32(reg, 1 << RSTMGR_RESET(reset));
+	else
+		clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
+}
+
+/*
+ * Write the reset manager register to cause reset.
+ */
+void reset_cpu(ulong addr)
+{
+	/* request a warm reset */
+	writel(ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK,
+	       &reset_manager_base->ctrl);
+	/*
+	 * infinite loop here as watchdog will trigger and reset
+	 * the processor
+	 */
+	while (1)
+		;
+}
+
+/*
+ * Disable all the peripherals except L4 watchdog0 and L4 Timer 0.
+ */
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void)
+{
+	unsigned mask_ecc_ocp =
+		ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
+		ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
+
+	/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
+	writel(~(ALT_RSTMGR_PER1MODRST_WD0_SET_MSK |
+	       ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK),
+	       &reset_manager_base->per1_mod_rst);
+	setbits_le32(&reset_manager_base->per0_mod_rst, ~mask_ecc_ocp);
+
+	/* Finally disable the ECC_OCP */
+	setbits_le32(&reset_manager_base->per0_mod_rst, mask_ecc_ocp);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_a10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_a10.h
new file mode 100644
index 0000000..3075abf
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_a10.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef	_SOCFPGA_RESET_MANAGER_A10_H_
+#define	_SOCFPGA_RESET_MANAGER_A10_H_
+
+#ifndef __ASSEMBLY__
+void reset_assert_all_peripherals_except_l4wd0_l4timer0(void);
+void socfpga_per_reset(u32 reset, int set);
+#endif /* __ASSEMBLY__ */
+
+struct socfpga_reset_manager {
+	u32 stat;
+	u32 ramstat;
+	u32 miscstat;
+	u32 ctrl;
+	u32 hdsken;
+	u32 hdskreq;
+	u32 hdskack;
+	u32 counts;
+	u32 mpu_mod_rst;
+	u32 per0_mod_rst;
+	u32 per1_mod_rst;
+	u32 brg_mod_rst;
+	u32 sys_mod_rst;
+	u32 coldmodrst;
+	u32 nrstmodrst;
+	u32 dbgmodrst;
+	u32 mpuwarmmask;
+	u32 per0warmmask;
+	u32 per1warmmask;
+	u32 brgwarmmask;
+	u32 syswarmmask;
+	u32 nrstwarmmask;
+	u32 l3warmmask;
+	u32 tststa;
+	u32 tstscratch;
+	u32 hdsktimeout;
+	u32 hmcintr;
+	u32 hmcintren;
+	u32 hmcintrens;
+	u32 hmcintrenr;
+	u32 hmcgpout;
+	u32 hmcgpin;
+};
+
+#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK	0x00000002
+#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK	0x00000001
+#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK	0x00000002
+#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK	0x00000004
+#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK	0x00000008
+#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK	0x00000010
+#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK	0x00000020
+#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK	0x00000040
+#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK	0x00000080
+#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK	0x00000100
+#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK	0x00000200
+#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK	0x00000400
+#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK	0x00000800
+#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK	0x00001000
+#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK	0x00002000
+#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK	0x00004000
+#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK	0x00008000
+#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK	0x00010000
+#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK	0x00020000
+#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK	0x00040000
+#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK	0x00080000
+#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK	0x00100000
+#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK	0x00200000
+#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK	0x00400000
+#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK	0x01000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK	0x02000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK	0x04000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK	0x08000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK	0x10000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK	0x20000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK	0x40000000
+#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK	0x80000000
+
+#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK	0x00000001
+#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK	0x00000002
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK	0x00000004
+#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK	0x00000008
+#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK	0x00000010
+#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK	0x00000020
+#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK	0x00000100
+#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK	0x00000200
+#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK	0x00000400
+#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK	0x00000800
+#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK	0x00001000
+#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK	0x00010000
+#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK	0x00020000
+#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK	0x01000000
+#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK	0x02000000
+#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK	0x04000000
+
+#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK	0x00000001
+#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK	0x00000002
+#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK	0x00000004
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK	0x00000008
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK	0x00000010
+#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK	0x00000020
+#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK	0x00000040
+
+#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK	0x00000001
+#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK	0x00000002
+#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK	0x00000004
+#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK	0x00000008
+
+/*
+ * Define a reset identifier, from which a permodrst bank ID
+ * and reset ID can be extracted using the subsequent macros
+ * RSTMGR_RESET() and RSTMGR_BANK().
+ */
+#define RSTMGR_BANK_OFFSET	8
+#define RSTMGR_BANK_MASK	0x7
+#define RSTMGR_RESET_OFFSET	0
+#define RSTMGR_RESET_MASK	0x1f
+#define RSTMGR_DEFINE(_bank, _offset)		\
+	((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)
+
+/* Extract reset ID from the reset identifier. */
+#define RSTMGR_RESET(_reset)			\
+	(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)
+
+/* Extract bank ID from the reset identifier. */
+#define RSTMGR_BANK(_reset)			\
+(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)
+
+/*
+ * SocFPGA Cyclone V/Arria V reset IDs, bank mapping is as follows:
+ * 0 ... mpumodrst
+ * 1 ... per0modrst
+ * 2 ... per1modrst
+ * 3 ... brgmodrst
+ * 4 ... sysmodrst
+ */
+#define RSTMGR_EMAC0		RSTMGR_DEFINE(1, 0)
+#define RSTMGR_EMAC1		RSTMGR_DEFINE(1, 1)
+#define RSTMGR_EMAC2		RSTMGR_DEFINE(1, 2)
+#define RSTMGR_WD0		RSTMGR_DEFINE(2, 0)
+#define RSTMGR_WD1		RSTMGR_DEFINE(2, 1)
+#define RSTMGR_L4SYSTIMER0	RSTMGR_DEFINE(2, 2)
+#define RSTMGR_L4SYSTIMER1	RSTMGR_DEFINE(2, 3)
+#define RSTMGR_SPTIMER0		RSTMGR_DEFINE(2, 4)
+#define RSTMGR_SPTIMER1		RSTMGR_DEFINE(2, 5)
+#define RSTMGR_UART0		RSTMGR_DEFINE(2, 16)
+#define RSTMGR_UART1		RSTMGR_DEFINE(2, 17)
+#define RSTMGR_SPIM0		RSTMGR_DEFINE(1, 17)
+#define RSTMGR_SPIM1		RSTMGR_DEFINE(1, 18)
+#define RSTMGR_QSPI		RSTMGR_DEFINE(1, 6)
+#define RSTMGR_SDMMC		RSTMGR_DEFINE(1, 7)
+#define RSTMGR_DMA		RSTMGR_DEFINE(1, 16)
+#define RSTMGR_DDRSCH		RSTMGR_DEFINE(3, 6)
+
+/* Create a human-readable reference to SoCFPGA reset. */
+#define SOCFPGA_RESET(_name)	RSTMGR_##_name
+
+#endif /* _SOCFPGA_RESET_MANAGER_A10_H_ */
-- 
2.6.2