From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ian Campbell <ijc+uboot@hellion.org.uk>
Date: Sat, 21 Nov 2015 15:48:29 +0000
Subject: [U-Boot] [PATCH] sunxi: Set AHB1 clock to PLL6/3 on all
 clock_sun6i.h using SoCs
In-Reply-To: <1448044323-4447-1-git-send-email-hdegoede@redhat.com>
References: <1448044323-4447-1-git-send-email-hdegoede@redhat.com>
Message-ID: <1448120909.13926.3.camel@hellion.org.uk>
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To: u-boot@lists.denx.de

On Fri, 2015-11-20 at 19:32 +0100, Hans de Goede wrote:
> According to the datasheets the max speed of AHB1 is 276 MHz, so
> setting it to PLL6 / 3 which gives us 200MHz everywhere is fine,
> and gives us a nice speed-up in certain workloads.
> 
> Suggested-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Hans de Goede <hdegoede@redhat.com>

I suppose you've tested this on at least one such board? In that case:
Acked-by: Ian Campbell <ijc@hellion.org.uk>

> ---
>  arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> index 09337a1..5c76275 100644
> --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> +++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
> @@ -220,11 +220,7 @@ struct sunxi_ccm_reg {
>  #define CCM_PLL11_CTRL_UPD		(0x1 << 30)
>  #define CCM_PLL11_CTRL_EN		(0x1 << 31)
>  
> -#if defined CONFIG_MACH_SUN8I_H3
>  #define AHB1_ABP1_DIV_DEFAULT		0x00003180 /*
> AHB1=PLL6/3,APB1=AHB1/2 */
> -#else
> -#define AHB1_ABP1_DIV_DEFAULT		0x00002020 /*
> AHB1=AXI/4, APB1=AHB1/2 */
> -#endif
>  
>  #define AXI_GATE_OFFSET_DRAM		0
>