From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Mon, 21 Dec 2015 22:37:28 +0800 Subject: [U-Boot] [PATCH] arm: socfpga: Actually enable L2 cache In-Reply-To: <201512211519.10016.marex@denx.de> References: <1450504730-10190-1-git-send-email-marex@denx.de> <201512211109.10822.marex@denx.de> <1450700703.2046.1.camel@altera.com> <201512211519.10016.marex@denx.de> Message-ID: <1450708648.2046.5.camel@altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, 2015-12-21 at 15:19 +0100, Marek Vasut wrote: > On Monday, December 21, 2015 at 01:25:03 PM, Chin Liang See wrote: > > On Mon, 2015-12-21 at 11:09 +0100, Marek Vasut wrote: > > > On Monday, December 21, 2015 at 10:50:50 AM, Chin Liang See > > > wrote: > > [..] > > > > > > Hmmm, here is the function for L2 cache within my development > > > > branch. > > > > Some of the latency tuning helps based on the benchmark result. > > > > Probably you can give it a try, Marek? > > > > > > > > void v7_outer_cache_enable(void) > > > > { > > > > > > > > /* disable the L2 cache */ > > > > writel(0, &pl310_regs_base->pl310_ctrl); > > > > > > > > /* enable BRESP, instruction and data prefetch, full > > > > line of > > > > > > > > zeroes */ > > > > > > > > setbits_le32(&pl310_regs_base->pl310_aux_ctrl, > > > > > > > > PL310_AUX_CTRL_FULL_LINE_ZERO_MASK | > > > > PL310_AUX_CTRL_DATA_PREFETCH_MASK | > > > > PL310_AUX_CTRL_INST_PREFETCH_MASK | > > > > PL310_AUX_CTRL_EARLY_BRESP_MASK); > > > > > > > > /* setup tag ram latency */ > > > > writel(0, &pl310_regs_base->pl310_tag_latency_ctrl); > > > > > > Are you _sure_ this is a good idea to set the latency to 0x0 ? > > > > Actually it still have 1 cycle of latency, just no additional > > And that's OK on socfpga ? I would've expected some latency here. Yup, Linux is using the same value too https://github.com/altera-opensource/linux-socfpga/blob/master/arch/arm /boot/dts/socfpga.dtsi Thanks Chin Liang > > Best regards, > Marek Vasut