[U-Boot] [PATCH 1/3] phy: atheros: Use ar8035_config for AR8031

[U-Boot] [PATCH 1/3] phy: atheros: Use ar8035_config for AR8031

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@nxp.com>

Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to
ar8021_config") selected 'ar8021_config' as the configuration function
for AR8031.

The correct would be to use 'ar8035_config' instead as AR8031/AR8035
have the same programming model and even share the same phy driver
in the linux kernel: drivers/net/phy/at803x.c.

Tested on a mx6qsabresd and wandboard, which now can work without
any PHY setup code in the board files.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
This is 2016.04 material.

Zhao Qiang, could you please test this on your platform?

 drivers/net/phy/atheros.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index d509e30..ba57b1a 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver =  {
 	.uid = 0x4dd074,
 	.mask = 0xffffffef,
 	.features = PHY_GBIT_FEATURES,
-	.config = ar8021_config,
+	.config = ar8035_config,
 	.startup = genphy_startup,
 	.shutdown = genphy_shutdown,
 };
-- 
1.9.1

[U-Boot] [PATCH 2/3] mx6sabresd: Simplify the Ethernet PHY configuration

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@nxp.com>

As per the AR8031 datasheet:

"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."

So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.

This results in a simpler code.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
This is 2016.04 material.

 board/freescale/mx6sabresd/mx6sabresd.c | 36 ++-------------------------------
 1 file changed, 2 insertions(+), 34 deletions(-)

diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 581c9d5..d20953d 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -94,8 +94,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
-	udelay(500);
+	mdelay(10);
 	gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+	udelay(100);
 }
 
 static iomux_v3_cfg_t const usdhc2_pads[] = {
@@ -340,39 +341,6 @@ int board_mmc_init(bd_t *bis)
 }
 #endif
 
-int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
-- 
1.9.1

[U-Boot] [PATCH 3/3] wandboard: Simplify the Ethernet PHY configuration

[Fabio Estevam]

From: Fabio Estevam <fabio.estevam@nxp.com>

As per the AR8031 datasheet:

"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."

So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.

This results in a simpler code.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
This is 2016.04 material.

 board/wandboard/wandboard.c | 36 ++----------------------------------
 1 file changed, 2 insertions(+), 34 deletions(-)

diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c
index 0af63d2..5fb7117 100644
--- a/board/wandboard/wandboard.c
+++ b/board/wandboard/wandboard.c
@@ -121,8 +121,9 @@ static void setup_iomux_enet(void)
 
 	/* Reset AR8031 PHY */
 	gpio_direction_output(ETH_PHY_RESET, 0);
-	udelay(500);
+	udelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
+	udelay(100);
 }
 
 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
@@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis)
 	return 0;
 }
 
-static int mx6_rgmii_rework(struct phy_device *phydev)
-{
-	unsigned short val;
-
-	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
-
-	/* introduce tx clock delay */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
-	val |= 0x0100;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
-
-	return 0;
-}
-
-int board_phy_config(struct phy_device *phydev)
-{
-	mx6_rgmii_rework(phydev);
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-
-	return 0;
-}
-
 #if defined(CONFIG_VIDEO_IPUV3)
 struct i2c_pads_info mx6q_i2c2_pad_info = {
 	.scl = {
-- 
1.9.1