[U-Boot] [PATCH v2 06/13] MIPS: Add support for Microchip PIC32MZ[DA] family.

Daniel Schwierzeck
2016-01-05T20:23:58Z

2016-01-04 15:01 GMT+01:00 Purna Chandra Mandal <purna.mandal@microchip.com>:
> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
>
> ---
>
> Changes in v2:
> - drop unnecessary board_early_init_f()
> - use LEAF(), END() macros for lowlevel_init
> - move initialization of board_init_f() argument to common start.S
> - move initdram() from board/microchip/ to mach-pic32/cpu.c
> - remove MIPS virtual address in favor of physical address in dts file
>
> arch/mips/cpu/start.S | 2 +
> arch/mips/dts/pic32mzda.dtsi | 64 +++++++++++++
> arch/mips/mach-pic32/Kconfig | 16 +++-
> arch/mips/mach-pic32/Makefile | 2 +-
> arch/mips/mach-pic32/cpu.c | 146 ++++++++++++++++++++++++++++++
> arch/mips/mach-pic32/include/mach/pic32.h | 3 +
> arch/mips/mach-pic32/lowlevel_init.S | 27 ++++++
> arch/mips/mach-pic32/reset.c | 36 ++++++++
> 8 files changed, 294 insertions(+), 2 deletions(-)
> create mode 100644 arch/mips/dts/pic32mzda.dtsi
> create mode 100644 arch/mips/mach-pic32/lowlevel_init.S
> create mode 100644 arch/mips/mach-pic32/reset.c
>
> diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S
> index e95cdca..a7e6722 100644
> --- a/arch/mips/cpu/start.S
> +++ b/arch/mips/cpu/start.S
> @@ -185,6 +185,8 @@ reset:
> PTR_ADDU t0, k0, GD_MALLOC_BASE # gd->malloc_base offset
> sw sp, 0(t0)
> #endif
> + /* Initialize args to zero. */
> + li a0, 0x0

please create a separate patch for this change. Also the code must be
compatible with MIPS64 now, so please do:

PTR_LI a0, 0

>
> PTR_LA t9, board_init_f
> jr t9
> diff --git a/arch/mips/dts/pic32mzda.dtsi b/arch/mips/dts/pic32mzda.dtsi
> new file mode 100644
> index 0000000..f518ba8
> --- /dev/null
> +++ b/arch/mips/dts/pic32mzda.dtsi
> @@ -0,0 +1,64 @@
> +/*
> + * Copyright 2015 Microchip Technology, Inc.
> + * Purna Chandra Mandal, <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/clock/microchip,clock.h>
> +#include "skeleton.dtsi"
> +
> +/ {
> + compatible = "microchip,pic32mzda", "microchip,pic32mz";
> +
> + cpus {
> + cpu at 0 {
> + compatible = "mips,mips14kc";
> + };
> + };
> +
> + clock: clk at 1f801200 {
> + compatible = "microchip,pic32mzda_clk";
> + reg = <0x1f801200 0x1000>;
> + clock-cells = <1>;
> + };
> +
> + uart1: serial at 1f822000 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822000 0x50>;
> + interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + clocks = <&clock PB2CLK>;
> + };
> +
> + uart2: serial at 1f822200 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822200 0x50>;
> + interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock PB2CLK>;
> + status = "disabled";
> + };
> +
> + uart6: serial at 1f822a00 {
> + compatible = "microchip,pic32mzda-uart";
> + reg = <0x1f822a00 0x50>;
> + interrupts = <188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clock PB2CLK>;
> + status = "disabled";
> + };
> +
> + evic: interrupt-controller at 1f810000 {
> + compatible = "microchip,pic32mzda-evic";
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + reg = <0x1f810000 0x1000>;
> + };
> +
> + pinctrl: pinctrl at 1f801400 {
> + compatible = "microchip,pic32mzda-pinctrl";
> + reg = <0x1f801400 0x100>, /* in */
> + <0x1f801500 0x200>; /* out */
> + status = "disabled";
> + };
> +};
> diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
> index 98b0b88..a394791 100644
> --- a/arch/mips/mach-pic32/Kconfig
> +++ b/arch/mips/mach-pic32/Kconfig
> @@ -2,11 +2,25 @@ menu "Microchip PIC32 platforms"
> depends on MACH_PIC32
>
> config SYS_SOC
> - default "none"
> + default "pic32mzda" if SOC_PIC32MZDA
>
> choice
> prompt "PIC32 SoC select"
>
> +config SOC_PIC32MZDA
> + bool "Microchip PIC32MZ[DA] family"
> + select SUPPORTS_LITTLE_ENDIAN
> + select SUPPORTS_CPU_MIPS32_R1
> + select SUPPORTS_CPU_MIPS32_R2
> + select SYS_MIPS_CACHE_INIT_RAM_LOAD

> + select MIPS_BOOT_CMDLINE_LEGACY
> + select MIPS_BOOT_FDT

those are user-selectable options and should not be enforced by the
SoC. But you can enable them in your defconfig.

> + select DM_SERIAL
> + select PIC32_SERIAL
> + select PIC32_PINCTRL
> + help
> + This supports Microchip PIC32MZ[DA] family of microcontrollers.
> +
> endchoice
>
> choice
> diff --git a/arch/mips/mach-pic32/Makefile b/arch/mips/mach-pic32/Makefile
> index cb42607..e321e65 100644
> --- a/arch/mips/mach-pic32/Makefile
> +++ b/arch/mips/mach-pic32/Makefile
> @@ -4,4 +4,4 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y = cpu.o
> +obj-y = cpu.o lowlevel_init.o reset.o
> \ No newline at end of file
> diff --git a/arch/mips/mach-pic32/cpu.c b/arch/mips/mach-pic32/cpu.c
> index 58fd3ab..7bd0f07 100644
> --- a/arch/mips/mach-pic32/cpu.c
> +++ b/arch/mips/mach-pic32/cpu.c
> @@ -6,8 +6,154 @@
> *
> */

your copyright and SPDX license identifier are missing

> #include <common.h>
> +#include <dm.h>
> +#include <clk.h>
> +#include <debug_uart.h>
> +#include <linux/compiler.h>
> +#include <asm/io.h>
> +#include <asm/mipsregs.h>
> +#include <mach/pic32.h>
> +#include <mach/ddr.h>
> +#include <dt-bindings/clock/microchip,clock.h>
>
> +/* Flash prefetch */
> +#define PRECON 0x00
> +#define PRECONCLR (PRECON + _CLR_OFFSET)
> +#define PRECONSET (PRECON + _SET_OFFSET)
> +
> +/* Flash ECCCON */
> +#define ECC_MASK 0x03
> +#define ECC_SHIFT 4
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +static ulong clk_get_cpu_rate(void)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> + if (ret) {
> + panic("uclass-clk: device not found\n");
> + return 0;
> + }
> +
> + return clk_get_rate(dev);
> +}
> +
> +/* initialize prefetch module related to cpu_clk */
> +static void init_prefetch(void)
> +{
> +#define _MHZ(x) ((x) * 1000000)

please do not define and undefine macros inside of function bodies.
You could define it once at the beginning of this file or in a header
file. You could also define the clock frequencies directly, e.g.

#define CLK_83_MHZ 83 * 1000 * 1000

> + void __iomem *base;
> + int v, nr_waits;
> + ulong rate;
> +
> + rate = clk_get_cpu_rate();
> +
> + /* get flash ECC type */
> + base = pic32_ioremap(PIC32_CFG_BASE);
> + v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
> + if (v < 2) {
> + if (rate < _MHZ(66))
> + nr_waits = 0;
> + else if (rate < _MHZ(133))
> + nr_waits = 1;
> + else
> + nr_waits = 2;
> + } else {
> + if (rate <= _MHZ(83))
> + nr_waits = 0;
> + else if (rate <= _MHZ(166))
> + nr_waits = 1;
> + else
> + nr_waits = 2;
> + }
> +
> + base = pic32_ioremap(PREFETCH_BASE);
> + writel(nr_waits, base + PRECON);
> +
> + /* Enable prefetch for all */
> + writel(0x30, base + PRECONSET);
> +#undef _MHZ
> +}
> +
> +/* arch specific CPU init after DM */
> +int arch_cpu_init_dm(void)
> +{
> + /* flash prefetch */
> + init_prefetch();
> + return 0;
> +}
> +
> +/* Un-gate DDR2 modules (gated by default) */
> +static void ddr2_pmd_ungate(void)
> +{
> + void __iomem *regs;
> +
> + regs = pic32_ioremap(PIC32_CFG_BASE);
> + writel(0, regs + PMD7);
> +}
> +
> +/* initialize the DDR2 Controller and DDR2 PHY */
> phys_size_t initdram(int board_type)
> {
> + ddr2_pmd_ungate();
> + ddr2_phy_init();
> + ddr2_ctrl_init();
> + return ddr2_calculate_size();
> +}
> +
> +int misc_init_r(void)
> +{
> + set_io_port_base(0);
> + return 0;
> +}
> +
> +#ifdef CONFIG_DISPLAY_BOARDINFO
> +const char *get_core_name(void)
> +{
> + u32 proc_id;
> + const char *str;
> +
> + proc_id = read_c0_prid();
> + switch (proc_id) {
> + case 0x19e28:
> + str = "PIC32MZ[DA]";
> + break;
> + default:
> + str = "UNKNOWN";
> + }
> +
> + return str;
> +}
> +#endif
> +
> +#ifdef CONFIG_CMD_CLK
> +int soc_clk_dump(void)
> +{
> +#define F_MHZ(x) ((x) / 1000000)
> + int i, ret;
> + struct udevice *dev;
> +
> + ret = uclass_get_device(UCLASS_CLK, 0, &dev);
> + if (ret) {
> + printf("clk-uclass not found\n");
> + return ret;
> + }
> +
> + printf("PLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, PLLCLK)));
> + printf("CPU Speed: %lu MHz\n", F_MHZ(clk_get_rate(dev)));
> + printf("MPLL Speed: %lu MHz\n", F_MHZ(clk_get_periph_rate(dev, MPLL)));
> +
> + for (i = PB1CLK; i <= PB7CLK; i++)
> + printf("PB%d Clock Speed: %lu MHz\n",
> + i - PB1CLK + 1, F_MHZ(clk_get_periph_rate(dev, i)));
> +
> + for (i = REF1CLK; i <= REF5CLK; i++)
> + printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
> + F_MHZ(clk_get_periph_rate(dev, i)));
> +#undef F_MHZ
> return 0;
> }
> +#endif
> diff --git a/arch/mips/mach-pic32/include/mach/pic32.h b/arch/mips/mach-pic32/include/mach/pic32.h
> index f618697..8d4b275 100644
> --- a/arch/mips/mach-pic32/include/mach/pic32.h
> +++ b/arch/mips/mach-pic32/include/mach/pic32.h
> @@ -76,4 +76,7 @@ static inline void __iomem *pic32_ioremap(phys_addr_t addr)
> return (void __iomem *)CKSEG1ADDR(addr);
> }
>
> +/* Core */
> +const char *get_core_name(void);
> +
> #endif /* __PIC32_REGS_H__ */
> diff --git a/arch/mips/mach-pic32/lowlevel_init.S b/arch/mips/mach-pic32/lowlevel_init.S
> new file mode 100644
> index 0000000..bff5553
> --- /dev/null
> +++ b/arch/mips/mach-pic32/lowlevel_init.S
> @@ -0,0 +1,27 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> +*/
> +
> +#include <config.h>
> +#include <asm/regdef.h>
> +#include <asm/mipsregs.h>
> +#include <asm/asm.h>
> +
> +LEAF(lowlevel_init)
> + /*
> + * Establish Cause
> + * (set IV bit)
> + */
> + li t1, 0x00800000
> + mtc0 t1, CP0_CAUSE
> +
> + /* Establish Wired (and Random) */
> + mtc0 zero, CP0_WIRED
> + nop
> +
> + jr ra
> + nop

please indent instructions in a delay slot with an extra space
character. That is convention for U-Boot MIPS assemby code.

> + END(lowlevel_init)
> diff --git a/arch/mips/mach-pic32/reset.c b/arch/mips/mach-pic32/reset.c
> new file mode 100644
> index 0000000..70467cb
> --- /dev/null
> +++ b/arch/mips/mach-pic32/reset.c
> @@ -0,0 +1,36 @@
> +/*
> + * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + *
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <mach/pic32.h>
> +
> +#define SYSKEY 0x0030
> +#define UNLOCK_KEY1 0xaa996655
> +#define UNLOCK_KEY2 0x556699aa
> +#define LOCK_KEY 0
> +
> +#define RSWRST 0x1250
> +
> +void _machine_restart(void)
> +{
> + void __iomem *base;
> +
> + base = pic32_ioremap(PIC32_CFG_BASE);
> +
> + /* unlock sequence */
> + writel(LOCK_KEY, base + SYSKEY);
> + writel(UNLOCK_KEY1, base + SYSKEY);
> + writel(UNLOCK_KEY2, base + SYSKEY);
> +
> + /* soft reset */
> + writel(0x1, base + RSWRST);
> + (void) readl(base + RSWRST);
> +
> + while (1)
> + ;
> +}
> --
> 1.8.3.1
>
>

--
- Daniel