* [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6
@ 2016-02-01 5:38 Peng Fan
2016-02-01 5:38 ` [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D Peng Fan
2016-02-02 0:05 ` [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Simon Glass
0 siblings, 2 replies; 6+ messages in thread
From: Peng Fan @ 2016-02-01 5:38 UTC (permalink / raw)
To: u-boot
Introduce pinctrl for i.MX6
1. pinctrl-imx.c is for common usage. It's used by i.MX6/7.
2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry.
3. To the pinctrl_ops implementation, only set_state is implemented.
To i.MX6/7, the pinctrl dts entry is as following:
&iomuxc {
pinctrl-names = "default";
pinctrl_csi1: csi1grp {
fsl,pins = <
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
>;
};
[.....]
};
there is no property named function or groups. So pinctrl_generic_set_state
can not be used here.
5. This driver is a simple implementation for i.mx iomux controller,
only parse the fsl,pins property and write value to registers.
6. With DEBUG enabled, we can see log when "i2c bus 0":
"
set_state_simple op missing
imx_pinctrl_set_state: i2c1grp
mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x14c val 0x10
select_input: offset 0x5d8 val 0x1
write config: offset 0x3bc val 0x7f
mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f
write mux: offset 0x148 val 0x10
select_input: offset 0x5d4 val 0x1
write config: offset 0x3b8 val 0x7f
"
this means imx6 pinctrl driver works as expected.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/nxp/Kconfig | 10 ++
drivers/pinctrl/nxp/Makefile | 2 +
drivers/pinctrl/nxp/pinctrl-imx.c | 224 +++++++++++++++++++++++++++++++++++++
drivers/pinctrl/nxp/pinctrl-imx.h | 59 ++++++++++
drivers/pinctrl/nxp/pinctrl-imx6.c | 41 +++++++
7 files changed, 338 insertions(+)
create mode 100644 drivers/pinctrl/nxp/Kconfig
create mode 100644 drivers/pinctrl/nxp/Makefile
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.c
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.h
create mode 100644 drivers/pinctrl/nxp/pinctrl-imx6.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 57e6142..9fd8f62 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -133,6 +133,7 @@ config PINCTRL_SANDBOX
endif
+source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 70d25dc..dcd20bf 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -5,6 +5,7 @@
obj-y += pinctrl-uclass.o
obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o
+obj-y += nxp/
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
new file mode 100644
index 0000000..2032588
--- /dev/null
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -0,0 +1,10 @@
+config PINCTRL_IMX
+ bool
+
+config PINCTRL_IMX6
+ bool "IMX6 pinctrl driver"
+ depends on ARCH_MX6
+ select DEVRES
+ select PINCTRL_IMX
+ help
+ Say Y here to enable the imx6ul pinctrl driver
diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile
new file mode 100644
index 0000000..7fd9850
--- /dev/null
+++ b/drivers/pinctrl/nxp/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
+obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c
new file mode 100644
index 0000000..09ffb1b
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <mapmem.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+ int node = config->of_offset;
+ const struct fdt_property *prop;
+ unsigned int *pin_data;
+ int npins, size, pin_size;
+ int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val;
+ int i, j = 0;
+
+ dev_dbg(dev, "%s: %s\n", __func__, config->name);
+
+ if (info->flags & SHARE_MUX_CONF_REG)
+ pin_size = SHARE_FSL_PIN_SIZE;
+ else
+ pin_size = FSL_PIN_SIZE;
+
+ prop = fdt_get_property(gd->fdt_blob, node, "fsl,pins", &size);
+ if (!prop) {
+ dev_err(dev, "No fsl,pins property in node %s\n", config->name);
+ return -EINVAL;
+ }
+
+ if (!size || size % pin_size) {
+ dev_err(dev, "Invalid fsl,pins property in node %s\n",
+ config->name);
+ return -EINVAL;
+ }
+
+ npins = size / pin_size;
+ pin_data = (unsigned int *)prop->data;
+
+ for (i = 0; i < npins; i++) {
+ mux_reg = fdt32_to_cpu(pin_data[j++]);
+
+ if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
+ mux_reg = -1;
+
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ conf_reg = mux_reg;
+ } else {
+ conf_reg = fdt32_to_cpu(pin_data[j++]);
+ if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg)
+ conf_reg = -1;
+ }
+
+ if ((mux_reg == -1) || (conf_reg == -1)) {
+ dev_err(dev, "Error mux_reg or conf_reg\n");
+ return -EINVAL;
+ }
+
+ input_reg = fdt32_to_cpu(pin_data[j++]);
+ mux_mode = fdt32_to_cpu(pin_data[j++]);
+ input_val = fdt32_to_cpu(pin_data[j++]);
+ config_val = fdt32_to_cpu(pin_data[j++]);
+
+ dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, "
+ "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n",
+ mux_reg, conf_reg, input_reg, mux_mode, input_val,
+ config_val);
+
+ if (config_val & IMX_PAD_SION)
+ mux_mode |= IOMUXC_CONFIG_SION;
+
+ config_val &= ~IMX_PAD_SION;
+
+ /* Set Mux */
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + mux_reg, 0x7 << 20,
+ mux_mode << 20);
+ } else {
+ writel(mux_mode, info->base + mux_reg);
+ }
+
+ dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg,
+ mux_mode);
+
+ /*
+ * Set select input
+ *
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+
+ if (input_val >> 24 == 0xff) {
+ u32 val = input_val;
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(info->base + input_reg);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, info->base + input_reg);
+ } else if (input_reg) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
+ if (info->input_sel_base)
+ writel(input_val, info->input_sel_base +
+ input_reg);
+ else
+ writel(input_val, info->base + input_reg);
+
+ dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n",
+ input_reg, input_val);
+ }
+
+ /* Set config */
+ if (!(config_val & IMX_NO_PAD_CTL)) {
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ clrsetbits_le32(info->base + conf_reg, 0xffff,
+ config_val);
+ } else {
+ writel(config_val, info->base + conf_reg);
+ }
+
+ dev_dbg(dev, "write config: offset 0x%x val 0x%x\n",
+ conf_reg, config_val);
+ }
+ }
+
+ return 0;
+}
+
+const struct pinctrl_ops imx_pinctrl_ops = {
+ .set_state = imx_pinctrl_set_state,
+};
+
+int imx_pinctrl_probe(struct udevice *dev,
+ struct imx_pinctrl_soc_info *info)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ int node = dev->of_offset, ret;
+ struct fdtdec_phandle_args arg;
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ if (!info) {
+ dev_err(dev, "wrong pinctrl info\n");
+ return -EINVAL;
+ }
+
+ priv->dev = dev;
+ priv->info = info;
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ info->base = map_sysmem(addr, size);
+ if (!info->base)
+ return -ENOMEM;
+ priv->info = info;
+
+ if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
+ ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
+ node, "fsl,input-sel",
+ NULL, 0, 0, &arg);
+ if (ret) {
+ dev_err(dev, "iomuxc fsl,input-sel property not found\n");
+ return -EINVAL;
+ }
+
+ addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
+ &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ info->input_sel_base = map_sysmem(addr, size);
+ if (!info->input_sel_base)
+ return -ENOMEM;
+ }
+
+ dev_info(dev, "initialized IMX pinctrl driver\n");
+
+ return 0;
+}
+
+int imx_pinctrl_remove(struct udevice *dev)
+{
+ struct imx_pinctrl_priv *priv = dev_get_priv(dev);
+ struct imx_pinctrl_soc_info *info = priv->info;
+
+ if (info->input_sel_base)
+ unmap_sysmem(info->input_sel_base);
+ if (info->base)
+ unmap_sysmem(info->base);
+
+ return 0;
+}
diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h
new file mode 100644
index 0000000..597c170
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx.h
@@ -0,0 +1,59 @@
+/*
+ * IMX pinmux core definitions
+ *
+ * Copyright (C) 2012-2015 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012 Linaro Ltd.
+ *
+ * Author: Dong Aisheng <dong.aisheng@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __DRIVERS_PINCTRL_IMX_H
+#define __DRIVERS_PINCTRL_IMX_H
+
+/**
+ * @base: the address to the controller in virtual memory
+ * @input_sel_base: the address of the select input in virtual memory.
+ * @flags: flags specific for each soc
+ */
+struct imx_pinctrl_soc_info {
+ void __iomem *base;
+ void __iomem *input_sel_base;
+ unsigned int flags;
+};
+
+/**
+ * @dev: a pointer back to containing device
+ * @info: the soc info
+ */
+struct imx_pinctrl_priv {
+ struct udevice *dev;
+ struct imx_pinctrl_soc_info *info;
+};
+
+extern const struct pinctrl_ops imx_pinctrl_ops;
+
+/* The bits in CONFIG cell defined in binding doc*/
+#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */
+#define IMX_PAD_SION 0x40000000 /* set SION */
+
+/*
+ * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and
+ * 1 u32 CONFIG, so 24 types in total for each pin.
+ */
+#define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
+
+#define SHARE_MUX_CONF_REG 0x1
+#define ZERO_OFFSET_VALID 0x2
+
+#define IOMUXC_CONFIG_SION (0x1 << 4)
+
+int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info);
+
+int imx_pinctrl_remove(struct udevice *dev);
+#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c
new file mode 100644
index 0000000..24f139e
--- /dev/null
+++ b/drivers/pinctrl/nxp/pinctrl-imx6.c
@@ -0,0 +1,41 @@
+
+/*
+ * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dm/device.h>
+#include <dm/pinctrl.h>
+
+#include "pinctrl-imx.h"
+
+static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info;
+
+static int imx6_pinctrl_probe(struct udevice *dev)
+{
+ struct imx_pinctrl_soc_info *info =
+ (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev);
+
+ return imx_pinctrl_probe(dev, info);
+}
+
+static const struct udevice_id imx6_pinctrl_match[] = {
+ { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(imx6_pinctrl) = {
+ .name = "imx6-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(imx6_pinctrl_match),
+ .probe = imx6_pinctrl_probe,
+ .remove = imx_pinctrl_remove,
+ .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv),
+ .ops = &imx_pinctrl_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.6.2
^ permalink raw reply related [flat|nested] 6+ messages in thread* [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D 2016-02-01 5:38 [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Peng Fan @ 2016-02-01 5:38 ` Peng Fan 2016-02-02 0:05 ` Simon Glass 2016-02-02 0:05 ` [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Simon Glass 1 sibling, 1 reply; 6+ messages in thread From: Peng Fan @ 2016-02-01 5:38 UTC (permalink / raw) To: u-boot Introudce i.MX7 pinctrl driver support. For now only i.MX7D supported. There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg and conf_reg can begin at 0. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> --- drivers/pinctrl/nxp/Kconfig | 8 ++++++++ drivers/pinctrl/nxp/Makefile | 1 + drivers/pinctrl/nxp/pinctrl-imx7.c | 42 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 51 insertions(+) create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7.c diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig index 2032588..a251d54 100644 --- a/drivers/pinctrl/nxp/Kconfig +++ b/drivers/pinctrl/nxp/Kconfig @@ -8,3 +8,11 @@ config PINCTRL_IMX6 select PINCTRL_IMX help Say Y here to enable the imx6ul pinctrl driver + +config PINCTRL_IMX7 + bool "IMX7 pinctrl driver" + depends on ARCH_MX7 + select DEVRES + select PINCTRL_IMX + help + Say Y here to enable the imx6ul pinctrl driver diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile index 7fd9850..0ee7f2f 100644 --- a/drivers/pinctrl/nxp/Makefile +++ b/drivers/pinctrl/nxp/Makefile @@ -1,2 +1,3 @@ obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o +obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c new file mode 100644 index 0000000..150ccf9 --- /dev/null +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c @@ -0,0 +1,42 @@ + +/* + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm/device.h> +#include <dm/pinctrl.h> + +#include "pinctrl-imx.h" + +static struct imx_pinctrl_soc_info imx7_pinctrl_soc_info; + +static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = { + .flags = ZERO_OFFSET_VALID, +}; + +static int imx7_pinctrl_probe(struct udevice *dev) +{ + struct imx_pinctrl_soc_info *info = + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); + + return imx_pinctrl_probe(dev, info); +} + +static const struct udevice_id imx7_pinctrl_match[] = { + { .compatible = "fsl,imx7d-iomuxc", .data = (ulong)&imx7_pinctrl_soc_info }, + { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = (ulong)&imx7_lpsr_pinctrl_soc_info }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(imx7_pinctrl) = { + .name = "imx7-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(imx7_pinctrl_match), + .probe = imx7_pinctrl_probe, + .remove = imx_pinctrl_remove, + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), + .ops = &imx_pinctrl_ops, + .flags = DM_FLAG_PRE_RELOC, +}; -- 2.6.2 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D 2016-02-01 5:38 ` [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D Peng Fan @ 2016-02-02 0:05 ` Simon Glass 2016-02-02 9:00 ` Peng Fan 0 siblings, 1 reply; 6+ messages in thread From: Simon Glass @ 2016-02-02 0:05 UTC (permalink / raw) To: u-boot Hi Peng, On 31 January 2016 at 22:38, Peng Fan <van.freenix@gmail.com> wrote: > Introudce i.MX7 pinctrl driver support. > For now only i.MX7D supported. > There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. > To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg > and conf_reg can begin at 0. > > Signed-off-by: Peng Fan <van.freenix@gmail.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > --- > drivers/pinctrl/nxp/Kconfig | 8 ++++++++ > drivers/pinctrl/nxp/Makefile | 1 + > drivers/pinctrl/nxp/pinctrl-imx7.c | 42 ++++++++++++++++++++++++++++++++++++++ > 3 files changed, 51 insertions(+) > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7.c Reviewed-by: Simon Glass <sjg@chromium.org> > > diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig > index 2032588..a251d54 100644 > --- a/drivers/pinctrl/nxp/Kconfig > +++ b/drivers/pinctrl/nxp/Kconfig > @@ -8,3 +8,11 @@ config PINCTRL_IMX6 > select PINCTRL_IMX > help > Say Y here to enable the imx6ul pinctrl driver > + > +config PINCTRL_IMX7 > + bool "IMX7 pinctrl driver" > + depends on ARCH_MX7 > + select DEVRES > + select PINCTRL_IMX > + help > + Say Y here to enable the imx6ul pinctrl driver Please add some help! > diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile > index 7fd9850..0ee7f2f 100644 > --- a/drivers/pinctrl/nxp/Makefile > +++ b/drivers/pinctrl/nxp/Makefile > @@ -1,2 +1,3 @@ > obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o > obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o > +obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o > diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c > new file mode 100644 > index 0000000..150ccf9 > --- /dev/null > +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c > @@ -0,0 +1,42 @@ > + > +/* > + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <dm/device.h> > +#include <dm/pinctrl.h> > + > +#include "pinctrl-imx.h" > + > +static struct imx_pinctrl_soc_info imx7_pinctrl_soc_info; > + > +static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = { > + .flags = ZERO_OFFSET_VALID, > +}; > + > +static int imx7_pinctrl_probe(struct udevice *dev) > +{ > + struct imx_pinctrl_soc_info *info = > + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); I think this should be platform data. > + > + return imx_pinctrl_probe(dev, info); > +} > + > +static const struct udevice_id imx7_pinctrl_match[] = { > + { .compatible = "fsl,imx7d-iomuxc", .data = (ulong)&imx7_pinctrl_soc_info }, > + { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = (ulong)&imx7_lpsr_pinctrl_soc_info }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(imx7_pinctrl) = { > + .name = "imx7-pinctrl", > + .id = UCLASS_PINCTRL, > + .of_match = of_match_ptr(imx7_pinctrl_match), > + .probe = imx7_pinctrl_probe, > + .remove = imx_pinctrl_remove, > + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), > + .ops = &imx_pinctrl_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; > -- > 2.6.2 > Regards, Simon ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D 2016-02-02 0:05 ` Simon Glass @ 2016-02-02 9:00 ` Peng Fan 0 siblings, 0 replies; 6+ messages in thread From: Peng Fan @ 2016-02-02 9:00 UTC (permalink / raw) To: u-boot Hi Simon, On Mon, Feb 01, 2016 at 05:05:18PM -0700, Simon Glass wrote: >Hi Peng, > >On 31 January 2016 at 22:38, Peng Fan <van.freenix@gmail.com> wrote: >> Introudce i.MX7 pinctrl driver support. >> For now only i.MX7D supported. >> There are two iomux controllers in i.MX7D, iomuxc and iomuxc_lpsr. >> To iomuxc_lpsr, ZERO_OFFSET_VALID is set, means offset of mux_reg >> and conf_reg can begin at 0. >> >> Signed-off-by: Peng Fan <van.freenix@gmail.com> >> Cc: Simon Glass <sjg@chromium.org> >> Cc: Stefano Babic <sbabic@denx.de> >> Cc: Fabio Estevam <fabio.estevam@nxp.com> >> --- >> drivers/pinctrl/nxp/Kconfig | 8 ++++++++ >> drivers/pinctrl/nxp/Makefile | 1 + >> drivers/pinctrl/nxp/pinctrl-imx7.c | 42 ++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 51 insertions(+) >> create mode 100644 drivers/pinctrl/nxp/pinctrl-imx7.c > >Reviewed-by: Simon Glass <sjg@chromium.org> > >> >> diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig >> index 2032588..a251d54 100644 >> --- a/drivers/pinctrl/nxp/Kconfig >> +++ b/drivers/pinctrl/nxp/Kconfig >> @@ -8,3 +8,11 @@ config PINCTRL_IMX6 >> select PINCTRL_IMX >> help >> Say Y here to enable the imx6ul pinctrl driver >> + >> +config PINCTRL_IMX7 >> + bool "IMX7 pinctrl driver" >> + depends on ARCH_MX7 >> + select DEVRES >> + select PINCTRL_IMX >> + help >> + Say Y here to enable the imx6ul pinctrl driver > >Please add some help! Will add more details in V2. > >> diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile >> index 7fd9850..0ee7f2f 100644 >> --- a/drivers/pinctrl/nxp/Makefile >> +++ b/drivers/pinctrl/nxp/Makefile >> @@ -1,2 +1,3 @@ >> obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o >> obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o >> +obj-$(CONFIG_PINCTRL_IMX7) += pinctrl-imx7.o >> diff --git a/drivers/pinctrl/nxp/pinctrl-imx7.c b/drivers/pinctrl/nxp/pinctrl-imx7.c >> new file mode 100644 >> index 0000000..150ccf9 >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/pinctrl-imx7.c >> @@ -0,0 +1,42 @@ >> + >> +/* >> + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <dm/device.h> >> +#include <dm/pinctrl.h> >> + >> +#include "pinctrl-imx.h" >> + >> +static struct imx_pinctrl_soc_info imx7_pinctrl_soc_info; >> + >> +static struct imx_pinctrl_soc_info imx7_lpsr_pinctrl_soc_info = { >> + .flags = ZERO_OFFSET_VALID, >> +}; >> + >> +static int imx7_pinctrl_probe(struct udevice *dev) >> +{ >> + struct imx_pinctrl_soc_info *info = >> + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); > >I think this should be platform data. Yeah. Thanks, Peng. > >> + >> + return imx_pinctrl_probe(dev, info); >> +} >> + >> +static const struct udevice_id imx7_pinctrl_match[] = { >> + { .compatible = "fsl,imx7d-iomuxc", .data = (ulong)&imx7_pinctrl_soc_info }, >> + { .compatible = "fsl,imx7d-iomuxc-lpsr", .data = (ulong)&imx7_lpsr_pinctrl_soc_info }, >> + { /* sentinel */ } >> +}; >> + >> +U_BOOT_DRIVER(imx7_pinctrl) = { >> + .name = "imx7-pinctrl", >> + .id = UCLASS_PINCTRL, >> + .of_match = of_match_ptr(imx7_pinctrl_match), >> + .probe = imx7_pinctrl_probe, >> + .remove = imx_pinctrl_remove, >> + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), >> + .ops = &imx_pinctrl_ops, >> + .flags = DM_FLAG_PRE_RELOC, >> +}; >> -- >> 2.6.2 >> > >Regards, >Simon ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 2016-02-01 5:38 [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Peng Fan 2016-02-01 5:38 ` [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D Peng Fan @ 2016-02-02 0:05 ` Simon Glass 2016-02-02 8:57 ` Peng Fan 1 sibling, 1 reply; 6+ messages in thread From: Simon Glass @ 2016-02-02 0:05 UTC (permalink / raw) To: u-boot Hi Peng, On 31 January 2016 at 22:38, Peng Fan <van.freenix@gmail.com> wrote: > Introduce pinctrl for i.MX6 > 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. > 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. > 3. To the pinctrl_ops implementation, only set_state is implemented. > To i.MX6/7, the pinctrl dts entry is as following: > &iomuxc { > pinctrl-names = "default"; > > pinctrl_csi1: csi1grp { > fsl,pins = < > MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 > MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 > MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 > >; > }; > > [.....] > }; > there is no property named function or groups. So pinctrl_generic_set_state > can not be used here. > 5. This driver is a simple implementation for i.mx iomux controller, > only parse the fsl,pins property and write value to registers. > 6. With DEBUG enabled, we can see log when "i2c bus 0": > " > set_state_simple op missing > imx_pinctrl_set_state: i2c1grp > mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f > write mux: offset 0x14c val 0x10 > select_input: offset 0x5d8 val 0x1 > write config: offset 0x3bc val 0x7f > mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f > write mux: offset 0x148 val 0x10 > select_input: offset 0x5d4 val 0x1 > write config: offset 0x3b8 val 0x7f > " > this means imx6 pinctrl driver works as expected. > > Signed-off-by: Peng Fan <van.freenix@gmail.com> > Cc: Simon Glass <sjg@chromium.org> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Fabio Estevam <fabio.estevam@nxp.com> > --- > drivers/pinctrl/Kconfig | 1 + > drivers/pinctrl/Makefile | 1 + > drivers/pinctrl/nxp/Kconfig | 10 ++ > drivers/pinctrl/nxp/Makefile | 2 + > drivers/pinctrl/nxp/pinctrl-imx.c | 224 +++++++++++++++++++++++++++++++++++++ > drivers/pinctrl/nxp/pinctrl-imx.h | 59 ++++++++++ > drivers/pinctrl/nxp/pinctrl-imx6.c | 41 +++++++ > 7 files changed, 338 insertions(+) > create mode 100644 drivers/pinctrl/nxp/Kconfig > create mode 100644 drivers/pinctrl/nxp/Makefile > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.c > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.h > create mode 100644 drivers/pinctrl/nxp/pinctrl-imx6.c > Reviewed-by: Simon Glass <sjg@chromium.org> Some questions and comments below. > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig > index 57e6142..9fd8f62 100644 > --- a/drivers/pinctrl/Kconfig > +++ b/drivers/pinctrl/Kconfig > @@ -133,6 +133,7 @@ config PINCTRL_SANDBOX > > endif > > +source "drivers/pinctrl/nxp/Kconfig" > source "drivers/pinctrl/uniphier/Kconfig" > > endmenu > diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile > index 70d25dc..dcd20bf 100644 > --- a/drivers/pinctrl/Makefile > +++ b/drivers/pinctrl/Makefile > @@ -5,6 +5,7 @@ > obj-y += pinctrl-uclass.o > obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o > > +obj-y += nxp/ > obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ > obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o > > diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig > new file mode 100644 > index 0000000..2032588 > --- /dev/null > +++ b/drivers/pinctrl/nxp/Kconfig > @@ -0,0 +1,10 @@ > +config PINCTRL_IMX > + bool > + > +config PINCTRL_IMX6 > + bool "IMX6 pinctrl driver" > + depends on ARCH_MX6 > + select DEVRES > + select PINCTRL_IMX > + help > + Say Y here to enable the imx6ul pinctrl driver Please can you add a few more details? What features does it support? What SoCs use it? > diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile > new file mode 100644 > index 0000000..7fd9850 > --- /dev/null > +++ b/drivers/pinctrl/nxp/Makefile > @@ -0,0 +1,2 @@ > +obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o > +obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c > new file mode 100644 > index 0000000..09ffb1b > --- /dev/null > +++ b/drivers/pinctrl/nxp/pinctrl-imx.c > @@ -0,0 +1,224 @@ > +/* > + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <common.h> > +#include <mapmem.h> > +#include <linux/io.h> > +#include <linux/err.h> > +#include <dm/device.h> > +#include <dm/pinctrl.h> > + > +#include "pinctrl-imx.h" > + > +DECLARE_GLOBAL_DATA_PTR; > + > +static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) > +{ > + struct imx_pinctrl_priv *priv = dev_get_priv(dev); > + struct imx_pinctrl_soc_info *info = priv->info; > + int node = config->of_offset; > + const struct fdt_property *prop; > + unsigned int *pin_data; > + int npins, size, pin_size; > + int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; > + int i, j = 0; > + > + dev_dbg(dev, "%s: %s\n", __func__, config->name); > + > + if (info->flags & SHARE_MUX_CONF_REG) > + pin_size = SHARE_FSL_PIN_SIZE; > + else > + pin_size = FSL_PIN_SIZE; > + > + prop = fdt_get_property(gd->fdt_blob, node, "fsl,pins", &size); fdt_getprop()? > + if (!prop) { > + dev_err(dev, "No fsl,pins property in node %s\n", config->name); > + return -EINVAL; > + } > + > + if (!size || size % pin_size) { > + dev_err(dev, "Invalid fsl,pins property in node %s\n", > + config->name); > + return -EINVAL; > + } > + > + npins = size / pin_size; > + pin_data = (unsigned int *)prop->data; > + > + for (i = 0; i < npins; i++) { > + mux_reg = fdt32_to_cpu(pin_data[j++]); Do you have the binding doc somewhere? You might consider using fdtget_get_int_array() if it helps. > + > + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) > + mux_reg = -1; > + > + if (info->flags & SHARE_MUX_CONF_REG) { > + conf_reg = mux_reg; > + } else { > + conf_reg = fdt32_to_cpu(pin_data[j++]); > + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) > + conf_reg = -1; > + } > + > + if ((mux_reg == -1) || (conf_reg == -1)) { > + dev_err(dev, "Error mux_reg or conf_reg\n"); > + return -EINVAL; > + } > + > + input_reg = fdt32_to_cpu(pin_data[j++]); > + mux_mode = fdt32_to_cpu(pin_data[j++]); > + input_val = fdt32_to_cpu(pin_data[j++]); > + config_val = fdt32_to_cpu(pin_data[j++]); > + > + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " > + "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", > + mux_reg, conf_reg, input_reg, mux_mode, input_val, > + config_val); > + > + if (config_val & IMX_PAD_SION) > + mux_mode |= IOMUXC_CONFIG_SION; > + > + config_val &= ~IMX_PAD_SION; > + > + /* Set Mux */ > + if (info->flags & SHARE_MUX_CONF_REG) { > + clrsetbits_le32(info->base + mux_reg, 0x7 << 20, > + mux_mode << 20); > + } else { > + writel(mux_mode, info->base + mux_reg); > + } > + > + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, > + mux_mode); > + > + /* > + * Set select input > + * > + * If the select input value begins with 0xff, it's a quirky > + * select input and the value should be interpreted as below. > + * 31 23 15 7 0 > + * | 0xff | shift | width | select | > + * It's used to work around the problem that the select > + * input for some pin is not implemented in the select > + * input register but in some general purpose register. > + * We encode the select input value, width and shift of > + * the bit field into input_val cell of pin function ID > + * in device tree, and then decode them here for setting > + * up the select input bits in general purpose register. > + */ > + > + if (input_val >> 24 == 0xff) { > + u32 val = input_val; > + u8 select = val & 0xff; > + u8 width = (val >> 8) & 0xff; > + u8 shift = (val >> 16) & 0xff; > + u32 mask = ((1 << width) - 1) << shift; > + /* > + * The input_reg[i] here is actually some IOMUXC general > + * purpose register, not regular select input register. > + */ > + val = readl(info->base + input_reg); > + val &= ~mask; > + val |= select << shift; > + writel(val, info->base + input_reg); > + } else if (input_reg) { > + /* > + * Regular select input register can never be at offset > + * 0, and we only print register value for regular case. > + */ > + if (info->input_sel_base) > + writel(input_val, info->input_sel_base + > + input_reg); > + else > + writel(input_val, info->base + input_reg); > + > + dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", > + input_reg, input_val); > + } > + > + /* Set config */ > + if (!(config_val & IMX_NO_PAD_CTL)) { > + if (info->flags & SHARE_MUX_CONF_REG) { > + clrsetbits_le32(info->base + conf_reg, 0xffff, > + config_val); > + } else { > + writel(config_val, info->base + conf_reg); > + } > + > + dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", > + conf_reg, config_val); > + } > + } > + > + return 0; > +} > + > +const struct pinctrl_ops imx_pinctrl_ops = { > + .set_state = imx_pinctrl_set_state, > +}; > + > +int imx_pinctrl_probe(struct udevice *dev, > + struct imx_pinctrl_soc_info *info) > +{ > + struct imx_pinctrl_priv *priv = dev_get_priv(dev); > + int node = dev->of_offset, ret; > + struct fdtdec_phandle_args arg; > + fdt_addr_t addr; > + fdt_size_t size; > + > + if (!info) { > + dev_err(dev, "wrong pinctrl info\n"); > + return -EINVAL; > + } > + > + priv->dev = dev; > + priv->info = info; > + > + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); > + > + if (addr == FDT_ADDR_T_NONE) > + return -EINVAL; > + > + info->base = map_sysmem(addr, size); > + if (!info->base) > + return -ENOMEM; > + priv->info = info; > + > + if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) { > + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, > + node, "fsl,input-sel", > + NULL, 0, 0, &arg); > + if (ret) { > + dev_err(dev, "iomuxc fsl,input-sel property not found\n"); > + return -EINVAL; > + } > + > + addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg", > + &size); > + if (addr == FDT_ADDR_T_NONE) > + return -EINVAL; > + > + info->input_sel_base = map_sysmem(addr, size); > + if (!info->input_sel_base) > + return -ENOMEM; This looks a little like something that a syscon or regmap might handle. Hard to tell from the code though. > + } > + > + dev_info(dev, "initialized IMX pinctrl driver\n"); > + > + return 0; > +} > + > +int imx_pinctrl_remove(struct udevice *dev) > +{ > + struct imx_pinctrl_priv *priv = dev_get_priv(dev); > + struct imx_pinctrl_soc_info *info = priv->info; > + > + if (info->input_sel_base) > + unmap_sysmem(info->input_sel_base); > + if (info->base) > + unmap_sysmem(info->base); > + > + return 0; > +} > diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h > new file mode 100644 > index 0000000..597c170 > --- /dev/null > +++ b/drivers/pinctrl/nxp/pinctrl-imx.h > @@ -0,0 +1,59 @@ > +/* > + * IMX pinmux core definitions > + * > + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. > + * Copyright (C) 2012 Linaro Ltd. > + * > + * Author: Dong Aisheng <dong.aisheng@linaro.org> > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. Can you use SPDX? > + */ > + > +#ifndef __DRIVERS_PINCTRL_IMX_H > +#define __DRIVERS_PINCTRL_IMX_H > + > +/** > + * @base: the address to the controller in virtual memory > + * @input_sel_base: the address of the select input in virtual memory. > + * @flags: flags specific for each soc > + */ > +struct imx_pinctrl_soc_info { > + void __iomem *base; > + void __iomem *input_sel_base; > + unsigned int flags; > +}; > + > +/** > + * @dev: a pointer back to containing device > + * @info: the soc info > + */ > +struct imx_pinctrl_priv { > + struct udevice *dev; > + struct imx_pinctrl_soc_info *info; > +}; > + > +extern const struct pinctrl_ops imx_pinctrl_ops; > + > +/* The bits in CONFIG cell defined in binding doc*/ > +#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ > +#define IMX_PAD_SION 0x40000000 /* set SION */ > + > +/* > + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and > + * 1 u32 CONFIG, so 24 types in total for each pin. > + */ > +#define FSL_PIN_SIZE 24 > +#define SHARE_FSL_PIN_SIZE 20 > + > +#define SHARE_MUX_CONF_REG 0x1 > +#define ZERO_OFFSET_VALID 0x2 > + > +#define IOMUXC_CONFIG_SION (0x1 << 4) > + > +int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); > + > +int imx_pinctrl_remove(struct udevice *dev); > +#endif /* __DRIVERS_PINCTRL_IMX_H */ > diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c > new file mode 100644 > index 0000000..24f139e > --- /dev/null > +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c > @@ -0,0 +1,41 @@ > + > +/* > + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include <dm/device.h> > +#include <dm/pinctrl.h> > + > +#include "pinctrl-imx.h" > + > +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info; > + > +static int imx6_pinctrl_probe(struct udevice *dev) > +{ > + struct imx_pinctrl_soc_info *info = > + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); > + Why are you passing this in? It doesn't seem to have any initialised data. Why not use dev_get_priv()? > + return imx_pinctrl_probe(dev, info); > +} > + > +static const struct udevice_id imx6_pinctrl_match[] = { > + { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, > + { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, > + { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, > + { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, > + { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(imx6_pinctrl) = { > + .name = "imx6-pinctrl", > + .id = UCLASS_PINCTRL, > + .of_match = of_match_ptr(imx6_pinctrl_match), > + .probe = imx6_pinctrl_probe, > + .remove = imx_pinctrl_remove, > + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), > + .ops = &imx_pinctrl_ops, > + .flags = DM_FLAG_PRE_RELOC, > +}; > -- > 2.6.2 > Regards, Simon ^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 2016-02-02 0:05 ` [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Simon Glass @ 2016-02-02 8:57 ` Peng Fan 0 siblings, 0 replies; 6+ messages in thread From: Peng Fan @ 2016-02-02 8:57 UTC (permalink / raw) To: u-boot Hi Simon, On Mon, Feb 01, 2016 at 05:05:05PM -0700, Simon Glass wrote: >Hi Peng, > >On 31 January 2016 at 22:38, Peng Fan <van.freenix@gmail.com> wrote: >> Introduce pinctrl for i.MX6 >> 1. pinctrl-imx.c is for common usage. It's used by i.MX6/7. >> 2. Add PINCTRL_IMX PINCTRL_IMX6 Kconfig entry. >> 3. To the pinctrl_ops implementation, only set_state is implemented. >> To i.MX6/7, the pinctrl dts entry is as following: >> &iomuxc { >> pinctrl-names = "default"; >> >> pinctrl_csi1: csi1grp { >> fsl,pins = < >> MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 >> MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 >> MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 >> >; >> }; >> >> [.....] >> }; >> there is no property named function or groups. So pinctrl_generic_set_state >> can not be used here. >> 5. This driver is a simple implementation for i.mx iomux controller, >> only parse the fsl,pins property and write value to registers. >> 6. With DEBUG enabled, we can see log when "i2c bus 0": >> " >> set_state_simple op missing >> imx_pinctrl_set_state: i2c1grp >> mux_reg 0x14c, conf_reg 0x3bc, input_reg 0x5d8, mux_mode 0x0, input_val 0x1, config_val 0x4000007f >> write mux: offset 0x14c val 0x10 >> select_input: offset 0x5d8 val 0x1 >> write config: offset 0x3bc val 0x7f >> mux_reg 0x148, conf_reg 0x3b8, input_reg 0x5d4, mux_mode 0x0, input_val 0x1, config_val 0x4000007f >> write mux: offset 0x148 val 0x10 >> select_input: offset 0x5d4 val 0x1 >> write config: offset 0x3b8 val 0x7f >> " >> this means imx6 pinctrl driver works as expected. >> >> Signed-off-by: Peng Fan <van.freenix@gmail.com> >> Cc: Simon Glass <sjg@chromium.org> >> Cc: Stefano Babic <sbabic@denx.de> >> Cc: Fabio Estevam <fabio.estevam@nxp.com> >> --- >> drivers/pinctrl/Kconfig | 1 + >> drivers/pinctrl/Makefile | 1 + >> drivers/pinctrl/nxp/Kconfig | 10 ++ >> drivers/pinctrl/nxp/Makefile | 2 + >> drivers/pinctrl/nxp/pinctrl-imx.c | 224 +++++++++++++++++++++++++++++++++++++ >> drivers/pinctrl/nxp/pinctrl-imx.h | 59 ++++++++++ >> drivers/pinctrl/nxp/pinctrl-imx6.c | 41 +++++++ >> 7 files changed, 338 insertions(+) >> create mode 100644 drivers/pinctrl/nxp/Kconfig >> create mode 100644 drivers/pinctrl/nxp/Makefile >> create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.c >> create mode 100644 drivers/pinctrl/nxp/pinctrl-imx.h >> create mode 100644 drivers/pinctrl/nxp/pinctrl-imx6.c >> > >Reviewed-by: Simon Glass <sjg@chromium.org> > >Some questions and comments below. > >> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig >> index 57e6142..9fd8f62 100644 >> --- a/drivers/pinctrl/Kconfig >> +++ b/drivers/pinctrl/Kconfig >> @@ -133,6 +133,7 @@ config PINCTRL_SANDBOX >> >> endif >> >> +source "drivers/pinctrl/nxp/Kconfig" >> source "drivers/pinctrl/uniphier/Kconfig" >> >> endmenu >> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile >> index 70d25dc..dcd20bf 100644 >> --- a/drivers/pinctrl/Makefile >> +++ b/drivers/pinctrl/Makefile >> @@ -5,6 +5,7 @@ >> obj-y += pinctrl-uclass.o >> obj-$(CONFIG_$(SPL_)PINCTRL_GENERIC) += pinctrl-generic.o >> >> +obj-y += nxp/ >> obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/ >> obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o >> >> diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig >> new file mode 100644 >> index 0000000..2032588 >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/Kconfig >> @@ -0,0 +1,10 @@ >> +config PINCTRL_IMX >> + bool >> + >> +config PINCTRL_IMX6 >> + bool "IMX6 pinctrl driver" >> + depends on ARCH_MX6 >> + select DEVRES >> + select PINCTRL_IMX >> + help >> + Say Y here to enable the imx6ul pinctrl driver > >Please can you add a few more details? What features does it support? >What SoCs use it? Ok. Will add more details in V2. > >> diff --git a/drivers/pinctrl/nxp/Makefile b/drivers/pinctrl/nxp/Makefile >> new file mode 100644 >> index 0000000..7fd9850 >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/Makefile >> @@ -0,0 +1,2 @@ >> +obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o >> +obj-$(CONFIG_PINCTRL_IMX6) += pinctrl-imx6.o >> diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c >> new file mode 100644 >> index 0000000..09ffb1b >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/pinctrl-imx.c >> @@ -0,0 +1,224 @@ >> +/* >> + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <common.h> >> +#include <mapmem.h> >> +#include <linux/io.h> >> +#include <linux/err.h> >> +#include <dm/device.h> >> +#include <dm/pinctrl.h> >> + >> +#include "pinctrl-imx.h" >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config) >> +{ >> + struct imx_pinctrl_priv *priv = dev_get_priv(dev); >> + struct imx_pinctrl_soc_info *info = priv->info; >> + int node = config->of_offset; >> + const struct fdt_property *prop; >> + unsigned int *pin_data; >> + int npins, size, pin_size; >> + int mux_reg, conf_reg, input_reg, input_val, mux_mode, config_val; >> + int i, j = 0; >> + >> + dev_dbg(dev, "%s: %s\n", __func__, config->name); >> + >> + if (info->flags & SHARE_MUX_CONF_REG) >> + pin_size = SHARE_FSL_PIN_SIZE; >> + else >> + pin_size = FSL_PIN_SIZE; >> + >> + prop = fdt_get_property(gd->fdt_blob, node, "fsl,pins", &size); > >fdt_getprop()? fdt_getprop returns void *, but I need to data entry of the property. So I use fdt_get_property and use prop->data[x]. Maybe I can use fdt_getprop, if I use fdtdec_get_int_array to get the data. > >> + if (!prop) { >> + dev_err(dev, "No fsl,pins property in node %s\n", config->name); >> + return -EINVAL; >> + } >> + >> + if (!size || size % pin_size) { >> + dev_err(dev, "Invalid fsl,pins property in node %s\n", >> + config->name); >> + return -EINVAL; >> + } >> + >> + npins = size / pin_size; >> + pin_data = (unsigned int *)prop->data; >> + >> + for (i = 0; i < npins; i++) { >> + mux_reg = fdt32_to_cpu(pin_data[j++]); > >Do you have the binding doc somewhere? Oh. I'll add the link to refer the linux devicetree binds here. > >You might consider using fdtget_get_int_array() if it helps. Ok. will try this. > >> + >> + if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg) >> + mux_reg = -1; >> + >> + if (info->flags & SHARE_MUX_CONF_REG) { >> + conf_reg = mux_reg; >> + } else { >> + conf_reg = fdt32_to_cpu(pin_data[j++]); >> + if (!(info->flags & ZERO_OFFSET_VALID) && !conf_reg) >> + conf_reg = -1; >> + } >> + >> + if ((mux_reg == -1) || (conf_reg == -1)) { >> + dev_err(dev, "Error mux_reg or conf_reg\n"); >> + return -EINVAL; >> + } >> + >> + input_reg = fdt32_to_cpu(pin_data[j++]); >> + mux_mode = fdt32_to_cpu(pin_data[j++]); >> + input_val = fdt32_to_cpu(pin_data[j++]); >> + config_val = fdt32_to_cpu(pin_data[j++]); >> + >> + dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, input_reg 0x%x, " >> + "mux_mode 0x%x, input_val 0x%x, config_val 0x%x\n", >> + mux_reg, conf_reg, input_reg, mux_mode, input_val, >> + config_val); >> + >> + if (config_val & IMX_PAD_SION) >> + mux_mode |= IOMUXC_CONFIG_SION; >> + >> + config_val &= ~IMX_PAD_SION; >> + >> + /* Set Mux */ >> + if (info->flags & SHARE_MUX_CONF_REG) { >> + clrsetbits_le32(info->base + mux_reg, 0x7 << 20, >> + mux_mode << 20); >> + } else { >> + writel(mux_mode, info->base + mux_reg); >> + } >> + >> + dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n", mux_reg, >> + mux_mode); >> + >> + /* >> + * Set select input >> + * >> + * If the select input value begins with 0xff, it's a quirky >> + * select input and the value should be interpreted as below. >> + * 31 23 15 7 0 >> + * | 0xff | shift | width | select | >> + * It's used to work around the problem that the select >> + * input for some pin is not implemented in the select >> + * input register but in some general purpose register. >> + * We encode the select input value, width and shift of >> + * the bit field into input_val cell of pin function ID >> + * in device tree, and then decode them here for setting >> + * up the select input bits in general purpose register. >> + */ >> + >> + if (input_val >> 24 == 0xff) { >> + u32 val = input_val; >> + u8 select = val & 0xff; >> + u8 width = (val >> 8) & 0xff; >> + u8 shift = (val >> 16) & 0xff; >> + u32 mask = ((1 << width) - 1) << shift; >> + /* >> + * The input_reg[i] here is actually some IOMUXC general >> + * purpose register, not regular select input register. >> + */ >> + val = readl(info->base + input_reg); >> + val &= ~mask; >> + val |= select << shift; >> + writel(val, info->base + input_reg); >> + } else if (input_reg) { >> + /* >> + * Regular select input register can never be at offset >> + * 0, and we only print register value for regular case. >> + */ >> + if (info->input_sel_base) >> + writel(input_val, info->input_sel_base + >> + input_reg); >> + else >> + writel(input_val, info->base + input_reg); >> + >> + dev_dbg(dev, "select_input: offset 0x%x val 0x%x\n", >> + input_reg, input_val); >> + } >> + >> + /* Set config */ >> + if (!(config_val & IMX_NO_PAD_CTL)) { >> + if (info->flags & SHARE_MUX_CONF_REG) { >> + clrsetbits_le32(info->base + conf_reg, 0xffff, >> + config_val); >> + } else { >> + writel(config_val, info->base + conf_reg); >> + } >> + >> + dev_dbg(dev, "write config: offset 0x%x val 0x%x\n", >> + conf_reg, config_val); >> + } >> + } >> + >> + return 0; >> +} >> + >> +const struct pinctrl_ops imx_pinctrl_ops = { >> + .set_state = imx_pinctrl_set_state, >> +}; >> + >> +int imx_pinctrl_probe(struct udevice *dev, >> + struct imx_pinctrl_soc_info *info) >> +{ >> + struct imx_pinctrl_priv *priv = dev_get_priv(dev); >> + int node = dev->of_offset, ret; >> + struct fdtdec_phandle_args arg; >> + fdt_addr_t addr; >> + fdt_size_t size; >> + >> + if (!info) { >> + dev_err(dev, "wrong pinctrl info\n"); >> + return -EINVAL; >> + } >> + >> + priv->dev = dev; >> + priv->info = info; >> + >> + addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); >> + >> + if (addr == FDT_ADDR_T_NONE) >> + return -EINVAL; >> + >> + info->base = map_sysmem(addr, size); >> + if (!info->base) >> + return -ENOMEM; >> + priv->info = info; >> + >> + if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) { >> + ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, >> + node, "fsl,input-sel", >> + NULL, 0, 0, &arg); >> + if (ret) { >> + dev_err(dev, "iomuxc fsl,input-sel property not found\n"); >> + return -EINVAL; >> + } >> + >> + addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg", >> + &size); >> + if (addr == FDT_ADDR_T_NONE) >> + return -EINVAL; >> + >> + info->input_sel_base = map_sysmem(addr, size); >> + if (!info->input_sel_base) >> + return -ENOMEM; > >This looks a little like something that a syscon or regmap might >handle. Hard to tell from the code though. The device tree: iomuxc_lpsr: iomuxc-lpsr at 302c0000 { compatible = "fsl,imx7d-iomuxc-lpsr"; reg = <0x302c0000 0x10000>; fsl,input-sel = <&iomuxc>; }; iomuxc: iomuxc at 30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; }; I followed the linux implementation. > >> + } >> + >> + dev_info(dev, "initialized IMX pinctrl driver\n"); >> + >> + return 0; >> +} >> + >> +int imx_pinctrl_remove(struct udevice *dev) >> +{ >> + struct imx_pinctrl_priv *priv = dev_get_priv(dev); >> + struct imx_pinctrl_soc_info *info = priv->info; >> + >> + if (info->input_sel_base) >> + unmap_sysmem(info->input_sel_base); >> + if (info->base) >> + unmap_sysmem(info->base); >> + >> + return 0; >> +} >> diff --git a/drivers/pinctrl/nxp/pinctrl-imx.h b/drivers/pinctrl/nxp/pinctrl-imx.h >> new file mode 100644 >> index 0000000..597c170 >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/pinctrl-imx.h >> @@ -0,0 +1,59 @@ >> +/* >> + * IMX pinmux core definitions >> + * >> + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. >> + * Copyright (C) 2012 Linaro Ltd. >> + * >> + * Author: Dong Aisheng <dong.aisheng@linaro.org> >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. > >Can you use SPDX? Will change this in V2. > >> + */ >> + >> +#ifndef __DRIVERS_PINCTRL_IMX_H >> +#define __DRIVERS_PINCTRL_IMX_H >> + >> +/** >> + * @base: the address to the controller in virtual memory >> + * @input_sel_base: the address of the select input in virtual memory. >> + * @flags: flags specific for each soc >> + */ >> +struct imx_pinctrl_soc_info { >> + void __iomem *base; >> + void __iomem *input_sel_base; >> + unsigned int flags; >> +}; >> + >> +/** >> + * @dev: a pointer back to containing device >> + * @info: the soc info >> + */ >> +struct imx_pinctrl_priv { >> + struct udevice *dev; >> + struct imx_pinctrl_soc_info *info; >> +}; >> + >> +extern const struct pinctrl_ops imx_pinctrl_ops; >> + >> +/* The bits in CONFIG cell defined in binding doc*/ >> +#define IMX_NO_PAD_CTL 0x80000000 /* no pin config need */ >> +#define IMX_PAD_SION 0x40000000 /* set SION */ >> + >> +/* >> + * Each pin represented in fsl,pins consists of 5 u32 PIN_FUNC_ID and >> + * 1 u32 CONFIG, so 24 types in total for each pin. >> + */ >> +#define FSL_PIN_SIZE 24 >> +#define SHARE_FSL_PIN_SIZE 20 >> + >> +#define SHARE_MUX_CONF_REG 0x1 >> +#define ZERO_OFFSET_VALID 0x2 >> + >> +#define IOMUXC_CONFIG_SION (0x1 << 4) >> + >> +int imx_pinctrl_probe(struct udevice *dev, struct imx_pinctrl_soc_info *info); >> + >> +int imx_pinctrl_remove(struct udevice *dev); >> +#endif /* __DRIVERS_PINCTRL_IMX_H */ >> diff --git a/drivers/pinctrl/nxp/pinctrl-imx6.c b/drivers/pinctrl/nxp/pinctrl-imx6.c >> new file mode 100644 >> index 0000000..24f139e >> --- /dev/null >> +++ b/drivers/pinctrl/nxp/pinctrl-imx6.c >> @@ -0,0 +1,41 @@ >> + >> +/* >> + * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com> >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#include <dm/device.h> >> +#include <dm/pinctrl.h> >> + >> +#include "pinctrl-imx.h" >> + >> +static struct imx_pinctrl_soc_info imx6_pinctrl_soc_info; >> + >> +static int imx6_pinctrl_probe(struct udevice *dev) >> +{ >> + struct imx_pinctrl_soc_info *info = >> + (struct imx_pinctrl_soc_info *)dev_get_driver_data(dev); >> + > >Why are you passing this in? It doesn't seem to have any initialised >data. Why not use dev_get_priv()? dev_get_priv returns struct imx_pinctrl_priv *. And I have this: struct imx_pinctrl_priv { struct udevice *dev; struct imx_pinctrl_soc_info *info; }; struct imx_pinctrl_soc_info { void __iomem *base; void __iomem *input_sel_base; unsigned int flags; }; i.MX7 needs the flags entry, but for now i.MX6 does not need the flags entry. But I think better to keep it. Thanks, Peng. > >> + return imx_pinctrl_probe(dev, info); >> +} >> + >> +static const struct udevice_id imx6_pinctrl_match[] = { >> + { .compatible = "fsl,imx6q-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, >> + { .compatible = "fsl,imx6dl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, >> + { .compatible = "fsl,imx6sl-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, >> + { .compatible = "fsl,imx6sx-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, >> + { .compatible = "fsl,imx6ul-iomuxc", .data = (ulong)&imx6_pinctrl_soc_info }, >> + { /* sentinel */ } >> +}; >> + >> +U_BOOT_DRIVER(imx6_pinctrl) = { >> + .name = "imx6-pinctrl", >> + .id = UCLASS_PINCTRL, >> + .of_match = of_match_ptr(imx6_pinctrl_match), >> + .probe = imx6_pinctrl_probe, >> + .remove = imx_pinctrl_remove, >> + .priv_auto_alloc_size = sizeof(struct imx_pinctrl_priv), >> + .ops = &imx_pinctrl_ops, >> + .flags = DM_FLAG_PRE_RELOC, >> +}; >> -- >> 2.6.2 >> > >Regards, >Simon ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-02-02 9:00 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2016-02-01 5:38 [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Peng Fan 2016-02-01 5:38 ` [U-Boot] [PATCH 2/2] pinctrl: imx: Support i.MX7D Peng Fan 2016-02-02 0:05 ` Simon Glass 2016-02-02 9:00 ` Peng Fan 2016-02-02 0:05 ` [U-Boot] [PATCH 1/2] pinctrl: imx: Introduce pinctrl driver for i.MX6 Simon Glass 2016-02-02 8:57 ` Peng Fan
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