[U-Boot] Problem with sf write on Arria 5.

[Chin Liang See <clsee@altera.com>]

On Wed, 2016-03-30 at 13:46 +0000, Bakhvalov, Denis (Nokia -
PL/Wroclaw) wrote:
> Hi Marek,
> 
> > Do "dcache off" and then update the flash again, it will work.
> > That's
> > the cache issue which we cannot track down.
> 
> Thank you for you quick support!
> 
> Maybe it's worth to invent a temporary solution?
> Because in other way users will face problems which are hard to find
> (I've been chasing this problem for 2 days).
> For example execute "dcache off" internally when sf write is called?
> 

I believe we can turn of the dcache as default for socfpga while effort
in progress to figure out the issue.

FYI, I was experimenting with L2 cache PL-310 registers but not
successful. I am trying to understand any issue between L2 cache and
the SDRAM. There is l2 cache sync after a flush but seems its not
working fine. Adding delay works but that not deemed a correct solution
(for USB case). Probably doing a virtual memory aliasing might
understand where the data was stuck.

Thanks
Chin Liang


> Best regards,
> Denis Bakhvalov