[U-Boot] Unaligned flush_dcache_range in axs101.c

[Alexey Brodkin <Alexey.Brodkin@synopsys.com>]

Hi Alex,

On Mon, 2016-04-04 at 09:38 +0200, Alexander Graf wrote:
> Hi Alexey,
> 
> Marek just pointed out to me the fact that flush_dcache_range on arm
> expects cache line aligned arguments. However, it seems like in axs101.c
> we have an unaligned cache flush:
> 
> ? flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
> 
> Could you please verify whether this is correct and if not just send a
> quick patch to fix it?

First this code is for support of Synopsys DesignWare AXS10x boards.
And AFAIK there's no such board that may sport ARM CPU instead or ARC.
So I'm wondering how did you bumped into that [issue?]?

Then I'm not really sure if there's a common requirement for arguments of
flush_dcache_range(). At least in "include/common.h" there's no comment about
that.

Personally I'd say this is up to each arch or SoC to implement?flush_dcache_range()
so it works properly on that particular hardware. I wouldn't like to
overcomplicate high-level stuff with low-level details such as cache lines etc
if that is not really necessary.

Please correct me if I'm missing something here.

-Alexey