From: Peng Fan <van.freenix@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] fsl_esdhc: Update clock enable bits for USDHC
Date: Tue, 26 Apr 2016 14:54:05 +0800 [thread overview]
Message-ID: <1461653646-22235-2-git-send-email-van.freenix@gmail.com> (raw)
In-Reply-To: <1461653646-22235-1-git-send-email-van.freenix@gmail.com>
From: Ye Li <ye.li@nxp.com>
The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
register. The driver uses RSTA to replace the clock gate off
operation. But this is not a good solution. This is because:
1. when using RSTA, we should wait this bit to clear by itself. This is not
implemeneted in the code.
2. After RSTA is set, it is recommended that the Host Driver reset the
external card and reinitialize it.
So in this patch, we change to use the vendorspec registers for these bits
operation.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: York Sun <york.sun@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Pantelis Antoniou <panto@antoniou-consulting.com>
---
drivers/mmc/fsl_esdhc.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 15cd419..b69c766 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -540,7 +540,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
clk = (pre_div << 8) | (div << 4);
#ifdef CONFIG_FSL_USDHC
- esdhc_setbits32(®s->sysctl, SYSCTL_RSTA);
+ esdhc_clrbits32(®s->vendorspec, VENDORSPEC_CKEN);
#else
esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN);
#endif
@@ -550,7 +550,7 @@ static void set_sysctl(struct mmc *mmc, uint clock)
udelay(10000);
#ifdef CONFIG_FSL_USDHC
- esdhc_clrbits32(®s->sysctl, SYSCTL_RSTA);
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
#else
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
#endif
@@ -645,6 +645,8 @@ static int esdhc_init(struct mmc *mmc)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
#endif
/* Set the initial clock speed */
@@ -766,6 +768,9 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv)
#ifndef CONFIG_FSL_USDHC
esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
| SYSCTL_IPGEN | SYSCTL_CKEN);
+#else
+ esdhc_setbits32(®s->vendorspec, VENDORSPEC_PEREN |
+ VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
#endif
writel(SDHCI_IRQ_EN_BITS, ®s->irqstaten);
--
2.6.2
next prev parent reply other threads:[~2016-04-26 6:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-26 6:54 [U-Boot] [PATCH 1/3] mmc: fsl: reset to normal boot mode when eMMC fast boot Peng Fan
2016-04-26 6:54 ` Peng Fan [this message]
2016-04-26 6:54 ` [U-Boot] [PATCH 3/3] mmc: fsl: introduce wp_enable Peng Fan
2016-06-14 23:01 ` Fabio Estevam
2016-06-14 23:23 ` Fabio Estevam
2016-06-15 1:17 ` Peng Fan
2016-06-15 1:35 ` Fabio Estevam
2016-06-15 4:04 ` york sun
2016-06-15 1:46 ` Fabio Estevam
2016-06-15 2:28 ` Peng Fan
2016-08-04 5:32 ` [U-Boot] [U-Boot, 1/3] mmc: fsl: reset to normal boot mode when eMMC fast boot Jaehoon Chung
2016-08-08 4:31 ` Peng Fan
2016-08-08 7:02 ` Jaehoon Chung
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