[U-Boot] [PATCH] armv8: ls1043ardb: invert irq pin polarity for AQR105 PHY

[shh.xie at gmail.com <shh.xie@gmail.com>]

From: Shaohui Xie <Shaohui.Xie@nxp.com>

To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by
setting relative bit in SCFG_INTPCR register, because AQR105 interrupt
is low active but GIC accepts high active.

Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
---
 board/freescale/ls1043ardb/ls1043ardb.c | 4 ++++
 include/configs/ls1043ardb.h            | 1 +
 2 files changed, 5 insertions(+)

diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index ec5fdbf..9e9f24d 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -84,6 +84,8 @@ int board_early_init_f(void)
 int board_init(void)
 {
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+
 
 	/*
 	 * Set CCI-400 control override register to enable barrier
@@ -106,6 +108,8 @@ int board_init(void)
 #ifdef CONFIG_U_QE
 	u_qe_init();
 #endif
+	/* invert AQR105 IRQ pins polarity */
+	out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
 
 	return 0;
 }
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h
index bc40b06..bfc1a5c 100644
--- a/include/configs/ls1043ardb.h
+++ b/include/configs/ls1043ardb.h
@@ -254,6 +254,7 @@
 #define CONFIG_PHY_VITESSE
 #define CONFIG_PHY_REALTEK
 #define CONFIG_PHY_AQUANTIA
+#define AQR105_IRQ_MASK			0x40000000
 
 #define RGMII_PHY1_ADDR			0x1
 #define RGMII_PHY2_ADDR			0x2
-- 
2.1.0.27.g96db324