[U-Boot] [PATCH 01/13] imx-common: introduce simpler macros for runtime dection

[U-Boot] [PATCH 01/13] imx-common: introduce simpler macros for runtime dection

[Peng Fan]

Introduce simpler macros for runtime cpu dection.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/include/asm/imx-common/sys_proto.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/include/asm/imx-common/sys_proto.h b/arch/arm/include/asm/imx-common/sys_proto.h
index 386c2dc..32f95b3 100644
--- a/arch/arm/include/asm/imx-common/sys_proto.h
+++ b/arch/arm/include/asm/imx-common/sys_proto.h
@@ -24,7 +24,15 @@
 #define is_cpu_type(cpu) (get_cpu_type() == cpu)
 #define is_soc_type(soc) (get_soc_type() == soc)
 
+#define is_mx6() (is_soc_type(MXC_SOC_MX6))
+#define is_mx7() (is_soc_type(MXC_SOC_MX7))
+
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
+#define is_mx6dq() (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+#define is_mx6sdl() (is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6DL))
+#define is_mx6sx() (is_cpu_type(MXC_CPU_MX6SX))
+#define is_mx6sl() (is_cpu_type(MXC_CPU_MX6SL))
+#define is_mx6ul() (is_cpu_type(MXC_CPU_MX6UL))
 
 u32 get_nr_cpus(void);
 u32 get_cpu_rev(void);
-- 
2.6.2

[U-Boot] [PATCH 02/13] imx: mx6: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx6/clock.c | 42 +++++++++++++++++++-----------------------
 arch/arm/cpu/armv7/mx6/ddr.c   | 10 ++++------
 arch/arm/cpu/armv7/mx6/soc.c   | 13 ++++++-------
 3 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index e6f2275..ff932aa 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -97,7 +97,7 @@ void enable_enet_clk(unsigned char enable)
 {
 	u32 mask, *addr;
 
-	if (is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6ul()) {
 		mask = MXC_CCM_CCGR3_ENET_MASK;
 		addr = &imx_ccm->CCGR3;
 	} else {
@@ -117,7 +117,7 @@ void enable_uart_clk(unsigned char enable)
 {
 	u32 mask;
 
-	if (is_cpu_type(MXC_CPU_MX6UL))
+	if (is_mx6ul())
 		mask = MXC_CCM_CCGR5_UART_MASK;
 	else
 		mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +168,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 			reg &= ~mask;
 		__raw_writel(reg, &imx_ccm->CCGR2);
 	} else {
-		if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+		if (is_mx6sx() || is_mx6ul()) {
 			mask = MXC_CCM_CCGR6_I2C4_MASK;
 			addr = &imx_ccm->CCGR6;
 		} else {
@@ -279,7 +279,7 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
 	switch (pll) {
 	case PLL_BUS:
-		if (!is_cpu_type(MXC_CPU_MX6UL)) {
+		if (!is_mx6ul()) {
 			if (pfd_num == 3) {
 				/* No PFD3 on PPL2 */
 				return 0;
@@ -379,8 +379,8 @@ static u32 get_ipg_per_clk(void)
 	u32 reg, perclk_podf;
 
 	reg = __raw_readl(&imx_ccm->cscmr1);
-	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6sl() || is_mx6sx() ||
+	    is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
 			return MXC_HCLK; /* OSC 24Mhz */
 	}
@@ -396,8 +396,7 @@ static u32 get_uart_clk(void)
 	u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
 	reg = __raw_readl(&imx_ccm->cscdr1);
 
-	if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
-	    is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
 			freq = MXC_HCLK;
 	}
@@ -416,8 +415,7 @@ static u32 get_cspi_clk(void)
 	cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
 		     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-	if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
-	    is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
 		if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
 			return MXC_HCLK / (cspi_podf + 1);
 	}
@@ -479,14 +477,13 @@ static u32 get_mmdc_ch0_clk(void)
 
 	u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-	    is_cpu_type(MXC_CPU_MX6SL)) {
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
 		podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
 			MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
 		if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
 			per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
 				MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
-			if (is_cpu_type(MXC_CPU_MX6SL)) {
+			if (is_mx6sl()) {
 				if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
 					freq = MXC_HCLK;
 				else
@@ -618,7 +615,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
 	debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-	if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+	if (!is_mx6sx() && !is_mx6ul()) {
 		debug("This chip not support lcd!\n");
 		return;
 	}
@@ -630,7 +627,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 			return;
 	}
 
-	if (is_cpu_type(MXC_CPU_MX6SX)) {
+	if (is_mx6sx()) {
 		reg = readl(&imx_ccm->cscdr2);
 		/* Can't change clocks when clock not from pre-mux */
 		if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
@@ -711,7 +708,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 				MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
 				((postd - 1) <<
 				 MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
-	} else if (is_cpu_type(MXC_CPU_MX6SX)) {
+	} else if (is_mx6sx()) {
 		/* Setting LCDIF2 for i.MX6SX */
 		if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
 			return;
@@ -737,7 +734,7 @@ int enable_lcdif_clock(u32 base_addr)
 	u32 reg = 0;
 	u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
 
-	if (is_cpu_type(MXC_CPU_MX6SX)) {
+	if (is_mx6sx()) {
 		if ((base_addr != LCDIF1_BASE_ADDR) &&
 		    (base_addr != LCDIF2_BASE_ADDR)) {
 			puts("Wrong LCD interface!\n");
@@ -752,7 +749,7 @@ int enable_lcdif_clock(u32 base_addr)
 			 MXC_CCM_CCGR3_DISP_AXI_MASK) :
 			(MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
 			 MXC_CCM_CCGR3_DISP_AXI_MASK);
-	} else if (is_cpu_type(MXC_CPU_MX6UL)) {
+	} else if (is_mx6ul()) {
 		if (base_addr != LCDIF1_BASE_ADDR) {
 			puts("Wrong LCD interface!\n");
 			return -EINVAL;
@@ -850,8 +847,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
 		reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
 	} else if (fec_id == 1) {
 		/* Only i.MX6SX/UL support ENET2 */
-		if (!(is_cpu_type(MXC_CPU_MX6SX) ||
-		      is_cpu_type(MXC_CPU_MX6UL)))
+		if (!(is_mx6sx() || is_mx6ul()))
 			return -EINVAL;
 		reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
 		reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -1044,7 +1040,7 @@ int enable_pcie_clock(void)
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF	0xa
 #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF	0xb
 
-	if (is_cpu_type(MXC_CPU_MX6SX))
+	if (is_mx6sx())
 		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_PCIE_REF;
 	else
 		lvds1_clk_sel = ANADIG_ANA_MISC1_LVDS1_CLK_SEL_SATA_REF;
@@ -1228,7 +1224,7 @@ static void disable_ldb_di_clock_sources(void)
 	/* Make sure PFDs are disabled@boot. */
 	reg = readl(&mxc_ccm->analog_pfd_528);
 	/* Cannot disable pll2_pfd2_396M, as it is the MMDC clock in iMX6DL */
-	if (is_cpu_type(MXC_CPU_MX6DL))
+	if (is_mx6sdl())
 		reg |= 0x80008080;
 	else
 		reg |= 0x80808080;
@@ -1251,7 +1247,7 @@ static void enable_ldb_di_clock_sources(void)
 	int reg;
 
 	reg = readl(&mxc_ccm->analog_pfd_528);
-	if (is_cpu_type(MXC_CPU_MX6DL))
+	if (is_mx6sdl())
 		reg &= ~(0x80008080);
 	else
 		reg &= ~(0x80808080);
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 1e7ae28..3cc8666 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -888,8 +888,7 @@ void mx6sdl_dram_iocfg(unsigned width,
 #define MR(val, ba, cmd, cs1) \
 	((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
 #define MMDC1(entry, value) do {					  \
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
-	    !is_cpu_type(MXC_CPU_MX6SL))				  \
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())			  \
 		mmdc1->entry = value;					  \
 	} while (0)
 
@@ -1197,12 +1196,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	u16 mem_speed = ddr3_cfg->mem_speed;
 
 	mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
-	if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
-	    !is_cpu_type(MXC_CPU_MX6SL))
+	if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_mx6dq()) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
@@ -1221,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
-	if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+	if (is_mx6dq()) {
 		if (clock > 528)
 			clock = 528; /* 528 MHz */
 	}
diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index aaa1adb..407f316 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -126,7 +126,7 @@ u32 get_cpu_speed_grade_hz(void)
 	val >>= OCOTP_CFG3_SPEED_SHIFT;
 	val &= 0x3;
 
-	if (is_cpu_type(MXC_CPU_MX6UL)) {
+	if (is_mx6ul()) {
 		if (val == OCOTP_CFG3_SPEED_528MHZ)
 			return 528000000;
 		else if (val == OCOTP_CFG3_SPEED_696MHZ)
@@ -138,14 +138,14 @@ u32 get_cpu_speed_grade_hz(void)
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_mx6dq())
 			return 1200000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_1GHZ:
 		return 996000000;
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_850MHZ:
-		if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+		if (is_mx6dq())
 			return 852000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_800MHZ:
@@ -293,7 +293,7 @@ static void clear_mmdc_ch_mask(void)
 	reg = readl(&mxc_ccm->ccdr);
 
 	/* Clear MMDC channel mask */
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL))
+	if (is_mx6sx() || is_mx6ul() || is_mx6sl())
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK);
 	else
 		reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK);
@@ -459,8 +459,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 	struct fuse_bank4_regs *fuse =
 			(struct fuse_bank4_regs *)bank->fuse_regs;
 
-	if ((is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) && 
-		dev_id == 1) {
+	if ((is_mx6sx() || is_mx6ul()) && dev_id == 1) {
 		u32 value = readl(&fuse->mac_addr2);
 		mac[0] = value >> 24 ;
 		mac[1] = value >> 16 ;
@@ -524,7 +523,7 @@ void s_init(void)
 	u32 mask528;
 	u32 reg, periph1, periph2;
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL))
+	if (is_mx6sx() || is_mx6ul())
 		return;
 
 	/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
-- 
2.6.2

[U-Boot] [PATCH 03/13] imx-common: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
Cc: "Beno?t Th?baudeau" <benoit.thebaudeau.dev@gmail.com>
---
 arch/arm/imx-common/hab.c      | 43 +++++++++++++-----------------------------
 arch/arm/imx-common/init.c     |  5 ++---
 arch/arm/imx-common/iomux-v3.c |  2 +-
 arch/arm/imx-common/sata.c     |  2 +-
 arch/arm/imx-common/timer.c    | 11 +++--------
 5 files changed, 20 insertions(+), 43 deletions(-)

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index 8bbcc22..a980688 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,60 +17,45 @@
 
 #define hab_rvt_report_event_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)	\
 )
 
 #define hab_rvt_report_status_p					\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)	\
 )
 
 #define hab_rvt_authenticate_image_p				\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)	\
 )
 
 #define hab_rvt_entry_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY)			\
 )
 
 #define hab_rvt_exit_p						\
 (								\
-	((is_cpu_type(MXC_CPU_MX6Q) ||				\
-	  is_cpu_type(MXC_CPU_MX6D)) &&				\
-	  (soc_rev() >= CHIP_REV_1_5)) ?			\
+	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
-	(is_cpu_type(MXC_CPU_MX6DL) &&				\
-	 (soc_rev() >= CHIP_REV_1_2)) ?				\
+	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT)			\
 )
@@ -424,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 			 */
 			/* Check MMU enabled */
 			if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
-				if (is_cpu_type(MXC_CPU_MX6Q) ||
-				    is_cpu_type(MXC_CPU_MX6D)) {
+				if (is_mx6dq()) {
 					/*
 					 * This won't work on Rev 1.0.0 of
 					 * i.MX6Q/D, since their ROM doesn't
@@ -434,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
 					 */
 					if (!is_mx6dqp())
 						writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6DL) ||
-					   is_cpu_type(MXC_CPU_MX6SOLO)) {
+				} else if (is_mx6sdl()) {
 					writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
-				} else if (is_cpu_type(MXC_CPU_MX6SL)) {
+				} else if (is_mx6sl()) {
 					writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
 				}
 			}
diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index 15dab1d..3d2ce3a 100644
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,7 +44,7 @@ void init_aips(void)
 	writel(0x00000000, &aips2->opacr3);
 	writel(0x00000000, &aips2->opacr4);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
+	if (is_mx6sx() || is_mx7()) {
 		/*
 		 * Set all MPROTx to be non-bufferable, trusted for R/W,
 		 * not forced to user-mode.
@@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable)
 	writew(enable, &wdog1->wmcr);
 	writew(enable, &wdog2->wmcr);
 
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
-			is_soc_type(MXC_SOC_MX7))
+	if (is_mx6sx() || is_mx6ul() || is_mx7())
 		writew(enable, &wdog3->wmcr);
 #ifdef CONFIG_MX7D
 	writew(enable, &wdog4->wmcr);
diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index 228d5f8..66137d1 100644
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
 
 #if defined(CONFIG_MX6QDL)
 	stride = 2;
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq())
 		p += 1;
 #else
 	stride = 1;
diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index d174a46..dd9698d 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq())
 		return 1;
 
 	ret = enable_sata_clock();
diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 92c7218..bea17f2 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
 static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
-	if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
-	    (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
-	     is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
-	     is_cpu_type(MXC_CPU_MX6UL))
+	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
+	    is_mx6sdl() || is_mx6sx() || is_mx6ul())
 		return 1;
 
 	return 0;
@@ -86,10 +84,7 @@ int timer_init(void)
 		i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
 
 		/* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
-		if (is_cpu_type(MXC_CPU_MX6DL) ||
-		    is_cpu_type(MXC_CPU_MX6SOLO) ||
-		    is_cpu_type(MXC_CPU_MX6SX) ||
-		    is_cpu_type(MXC_CPU_MX6UL)) {
+		if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
 			i |= GPTCR_24MEN;
 
 			/* Produce 3Mhz clock */
-- 
2.6.2

[U-Boot] [PATCH 04/13] imx: mx6: ddr: support i.MX6D/QPlus

[Peng Fan]

Support i.MX6D/QPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx6/ddr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 3cc8666..f151eec 100644
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -1200,7 +1200,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 		mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
 
 	/* Limit mem_speed for MX6D/MX6Q */
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		if (mem_speed > 1066)
 			mem_speed = 1066; /* 1066 MT/s */
 
@@ -1219,7 +1219,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
 	 * Data rate of 1066 MT/s requires 533 MHz DDR3 clock, but MX6D/Q supports
 	 * up to 528 MHz, so reduce the clock to fit chip specs
 	 */
-	if (is_mx6dq()) {
+	if (is_mx6dq() || is_mx6dqp()) {
 		if (clock > 528)
 			clock = 528; /* 528 MHz */
 	}
-- 
2.6.2

[U-Boot] [PATCH 05/13] imx: mx6: correct get_cpu_speed_grade_hz for i.MX6DQP

[Peng Fan]

Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we
will get wrong speed grade info i.MX6DQP.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/cpu/armv7/mx6/soc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 407f316..88fcfdc 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -138,14 +138,14 @@ u32 get_cpu_speed_grade_hz(void)
 	switch (val) {
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_1P2GHZ:
-		if (is_mx6dq())
+		if (is_mx6dq() || is_mx6dqp())
 			return 1200000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_1GHZ:
 		return 996000000;
 	/* Valid for IMX6DQ */
 	case OCOTP_CFG3_SPEED_850MHZ:
-		if (is_mx6dq())
+		if (is_mx6dq() || is_mx6dqp())
 			return 852000000;
 	/* Valid for IMX6SX/IMX6SDL/IMX6DQ */
 	case OCOTP_CFG3_SPEED_800MHZ:
-- 
2.6.2

[U-Boot] [PATCH 06/13] imx-common: hab: support i.MX6DQPlus

[Peng Fan]

Support i.MX6DQPlus, otherwise wrong hab address will be used
for i.MX6QDPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/imx-common/hab.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
index a980688..6731825 100644
--- a/arch/arm/imx-common/hab.c
+++ b/arch/arm/imx-common/hab.c
@@ -17,6 +17,8 @@
 
 #define hab_rvt_report_event_p					\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :	\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -26,6 +28,8 @@
 
 #define hab_rvt_report_status_p					\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -35,6 +39,8 @@
 
 #define hab_rvt_authenticate_image_p				\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -44,6 +50,8 @@
 
 #define hab_rvt_entry_p						\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :		\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
@@ -53,6 +61,8 @@
 
 #define hab_rvt_exit_p						\
 (								\
+	(is_mx6dqp()) ?						\
+	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	(is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?		\
 	((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :			\
 	(is_mx6sdl() &&	(soc_rev() >= CHIP_REV_1_2)) ?		\
-- 
2.6.2

[U-Boot] [PATCH 07/13] imx-common: sata: return failure if not i.MX6DQPlus

[Peng Fan]

The i.MX6DQPlus support sata interface, we should not
return failure when CPU is i.MX6DQPlus.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/imx-common/sata.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
index dd9698d..acf9831 100644
--- a/arch/arm/imx-common/sata.c
+++ b/arch/arm/imx-common/sata.c
@@ -15,7 +15,7 @@ int setup_sata(void)
 	struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	int ret;
 
-	if (!is_mx6dq())
+	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 
 	ret = enable_sata_clock();
-- 
2.6.2

[U-Boot] [PATCH 08/13] imx-common: timer: support i.MX6DQPlus

[Peng Fan]

To i.MX6DQPlus, osc can be choosed as the source of gpt, so
add i.MX6DQPlus support in gpt_has_clk_source_osc.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/imx-common/timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index bea17f2..a01590c 100644
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -44,7 +44,7 @@ static inline int gpt_has_clk_source_osc(void)
 {
 #if defined(CONFIG_MX6)
 	if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
-	    is_mx6sdl() || is_mx6sx() || is_mx6ul())
+	    is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul())
 		return 1;
 
 	return 0;
-- 
2.6.2

[U-Boot] [PATCH 09/13] mtd: nand: mxs: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Scott Wood <oss@buserror.net>
---
 drivers/mtd/nand/mxs_nand.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index b5bbd88..5528d4b 100644
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
 	int max_ecc_strength_supported;
 
 	/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
-	if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
+	if (is_mx6sx() || is_mx7())
 		max_ecc_strength_supported = 62;
 	else
 		max_ecc_strength_supported = 40;
-- 
2.6.2

[U-Boot] [PATCH 10/13] ocotp: mxc: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 drivers/misc/mxc_ocotp.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/mxc_ocotp.c b/drivers/misc/mxc_ocotp.c
index 65ff815..38344e8 100644
--- a/drivers/misc/mxc_ocotp.c
+++ b/drivers/misc/mxc_ocotp.c
@@ -95,9 +95,9 @@ u32 fuse_bank_physical(int index)
 {
 	u32 phy_index;
 
-	if (is_cpu_type(MXC_CPU_MX6SL)) {
+	if (is_mx6sl()) {
 		phy_index = index;
-	} else if (is_cpu_type(MXC_CPU_MX6UL)) {
+	} else if (is_mx6ul()) {
 		if (index >= 6)
 			phy_index = fuse_bank_physical(5) + (index - 6) + 3;
 		else
-- 
2.6.2

[U-Boot] [PATCH 11/13] net: fec_mxc: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
---
 drivers/net/fec_mxc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 3340dd2..360f8e4 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -566,7 +566,7 @@ static int fec_init(struct eth_device *dev, bd_t* bd)
 
 
 	/* Do not access reserved register for i.MX6UL */
-	if (!is_cpu_type(MXC_CPU_MX6UL)) {
+	if (!is_mx6ul()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
-- 
2.6.2

[U-Boot] [PATCH 12/13] block: dwc_ahsata: support i.MX6DQPlus

[Peng Fan]

i.MX6DQPlus support sata interface, so not return failure
when CPU is i.MX6DQPlus.

In this patch, also use simpler runtime cpu dections macros to replace
is_cpu_type.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tang Yuantian <Yuantian.Tang@freescale.com>
Cc: Shaohui Xie <Shaohui.Xie@freescale.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
---
 drivers/block/dwc_ahsata.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 6ec52a9..6056fe5 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -563,7 +563,7 @@ int init_sata(int dev)
 	struct ahci_probe_ent *probe_ent = NULL;
 
 #if defined(CONFIG_MX6)
-	if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+	if (!is_mx6dq() && !is_mx6dqp())
 		return 1;
 #endif
 	if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
-- 
2.6.2

[U-Boot] [PATCH 13/13] board: mx6sabresd/auto: use simpler runtime cpu dection macros

[Peng Fan]

Use simpler runtime cpu dection macros.

Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 board/freescale/mx6qsabreauto/mx6qsabreauto.c | 4 ++--
 board/freescale/mx6sabresd/mx6sabresd.c       | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
index c2e9c57..0712f08 100644
--- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c
+++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c
@@ -625,9 +625,9 @@ int board_late_init(void)
 
 	if (is_mx6dqp())
 		setenv("board_rev", "MX6QP");
-	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	else if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
-	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	else if (is_mx6sdl())
 		setenv("board_rev", "MX6DL");
 #endif
 
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c
index 2319354..54ba36b 100644
--- a/board/freescale/mx6sabresd/mx6sabresd.c
+++ b/board/freescale/mx6sabresd/mx6sabresd.c
@@ -649,9 +649,9 @@ int board_late_init(void)
 
 	if (is_mx6dqp())
 		setenv("board_rev", "MX6QP");
-	else if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D))
+	else if (is_mx6dq())
 		setenv("board_rev", "MX6Q");
-	else if (is_cpu_type(MXC_CPU_MX6DL) || is_cpu_type(MXC_CPU_MX6SOLO))
+	else if (is_mx6sdl())
 		setenv("board_rev", "MX6DL");
 #endif
 
-- 
2.6.2

[U-Boot] [PATCH 03/13] imx-common: use simpler runtime cpu dection macros

[Benoît Thébaudeau]

Dear Peng Fan,

On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote:
> Use simpler runtime cpu dection macros.
>
> Signed-off-by: Peng Fan <van.freenix@gmail.com>
> Cc: Stefano Babic <sbabic@denx.de>
> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
> Cc: "Beno?t Th?baudeau" <benoit.thebaudeau.dev@gmail.com>
> ---
>  arch/arm/imx-common/hab.c      | 43 +++++++++++++-----------------------------
>  arch/arm/imx-common/init.c     |  5 ++---
>  arch/arm/imx-common/iomux-v3.c |  2 +-
>  arch/arm/imx-common/sata.c     |  2 +-
>  arch/arm/imx-common/timer.c    | 11 +++--------
>  5 files changed, 20 insertions(+), 43 deletions(-)
>
> diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
> index 8bbcc22..a980688 100644
> --- a/arch/arm/imx-common/hab.c
> +++ b/arch/arm/imx-common/hab.c
> @@ -17,60 +17,45 @@
>
>  #define hab_rvt_report_event_p                                 \
>  (                                                              \
> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>         ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \

This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is
this on purpose? If so, then it means that there was something
unrelated to this patch that was wrong in this code for
MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before
this one. If not, then an is_mx6dl() macro should be introduced.

>         ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
>         ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)        \
>  )
>
>  #define hab_rvt_report_status_p                                        \
>  (                                                              \
> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>         ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \

Ditto.

>         ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
>         ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)      \
>  )
>
>  #define hab_rvt_authenticate_image_p                           \
>  (                                                              \
> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>         ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \

Ditto.

>         ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
>         ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)    \
>  )
>
>  #define hab_rvt_entry_p                                                \
>  (                                                              \
> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>         ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \

Ditto.

>         ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) :                \
>         ((hab_rvt_entry_t *)HAB_RVT_ENTRY)                      \
>  )
>
>  #define hab_rvt_exit_p                                         \
>  (                                                              \
> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>         ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \

Ditto.

>         ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) :                  \
>         ((hab_rvt_exit_t *)HAB_RVT_EXIT)                        \
>  )
> @@ -424,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
>                          */
>                         /* Check MMU enabled */
>                         if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
> -                               if (is_cpu_type(MXC_CPU_MX6Q) ||
> -                                   is_cpu_type(MXC_CPU_MX6D)) {
> +                               if (is_mx6dq()) {
>                                         /*
>                                          * This won't work on Rev 1.0.0 of
>                                          * i.MX6Q/D, since their ROM doesn't
> @@ -434,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
>                                          */
>                                         if (!is_mx6dqp())
>                                                 writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
> -                               } else if (is_cpu_type(MXC_CPU_MX6DL) ||
> -                                          is_cpu_type(MXC_CPU_MX6SOLO)) {
> +                               } else if (is_mx6sdl()) {
>                                         writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
> -                               } else if (is_cpu_type(MXC_CPU_MX6SL)) {
> +                               } else if (is_mx6sl()) {
>                                         writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
>                                 }
>                         }
> diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
> index 15dab1d..3d2ce3a 100644
> --- a/arch/arm/imx-common/init.c
> +++ b/arch/arm/imx-common/init.c
> @@ -44,7 +44,7 @@ void init_aips(void)
>         writel(0x00000000, &aips2->opacr3);
>         writel(0x00000000, &aips2->opacr4);
>
> -       if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) {
> +       if (is_mx6sx() || is_mx7()) {
>                 /*
>                  * Set all MPROTx to be non-bufferable, trusted for R/W,
>                  * not forced to user-mode.
> @@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable)
>         writew(enable, &wdog1->wmcr);
>         writew(enable, &wdog2->wmcr);
>
> -       if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
> -                       is_soc_type(MXC_SOC_MX7))
> +       if (is_mx6sx() || is_mx6ul() || is_mx7())
>                 writew(enable, &wdog3->wmcr);
>  #ifdef CONFIG_MX7D
>         writew(enable, &wdog4->wmcr);
> diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
> index 228d5f8..66137d1 100644
> --- a/arch/arm/imx-common/iomux-v3.c
> +++ b/arch/arm/imx-common/iomux-v3.c
> @@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
>
>  #if defined(CONFIG_MX6QDL)
>         stride = 2;
> -       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
> +       if (!is_mx6dq())
>                 p += 1;
>  #else
>         stride = 1;
> diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c
> index d174a46..dd9698d 100644
> --- a/arch/arm/imx-common/sata.c
> +++ b/arch/arm/imx-common/sata.c
> @@ -15,7 +15,7 @@ int setup_sata(void)
>         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
>         int ret;
>
> -       if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
> +       if (!is_mx6dq())
>                 return 1;
>
>         ret = enable_sata_clock();
> diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
> index 92c7218..bea17f2 100644
> --- a/arch/arm/imx-common/timer.c
> +++ b/arch/arm/imx-common/timer.c
> @@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR;
>  static inline int gpt_has_clk_source_osc(void)
>  {
>  #if defined(CONFIG_MX6)
> -       if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
> -           (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
> -            is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
> -            is_cpu_type(MXC_CPU_MX6UL))
> +       if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||

The extra parentheses around is_mx6dq() can be removed.

> +           is_mx6sdl() || is_mx6sx() || is_mx6ul())
>                 return 1;
>
>         return 0;
> @@ -86,10 +84,7 @@ int timer_init(void)
>                 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
>
>                 /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
> -               if (is_cpu_type(MXC_CPU_MX6DL) ||
> -                   is_cpu_type(MXC_CPU_MX6SOLO) ||
> -                   is_cpu_type(MXC_CPU_MX6SX) ||
> -                   is_cpu_type(MXC_CPU_MX6UL)) {
> +               if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) {
>                         i |= GPTCR_24MEN;
>
>                         /* Produce 3Mhz clock */
> --
> 2.6.2

Best regards,
Beno?t

[U-Boot] [PATCH 03/13] imx-common: use simpler runtime cpu dection macros

[Peng Fan]

Hi Beno?t,

On Fri, May 20, 2016 at 01:02:10AM +0200, Beno?t Th?baudeau wrote:
>Dear Peng Fan,
>
>On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote:
>> Use simpler runtime cpu dection macros.
>>
>> Signed-off-by: Peng Fan <van.freenix@gmail.com>
>> Cc: Stefano Babic <sbabic@denx.de>
>> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
>> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
>> Cc: "Beno?t Th?baudeau" <benoit.thebaudeau.dev@gmail.com>
>> ---
>>  arch/arm/imx-common/hab.c      | 43 +++++++++++++-----------------------------
>>  arch/arm/imx-common/init.c     |  5 ++---
>>  arch/arm/imx-common/iomux-v3.c |  2 +-
>>  arch/arm/imx-common/sata.c     |  2 +-
>>  arch/arm/imx-common/timer.c    | 11 +++--------
>>  5 files changed, 20 insertions(+), 43 deletions(-)
>>
>> diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
>> index 8bbcc22..a980688 100644
>> --- a/arch/arm/imx-common/hab.c
>> +++ b/arch/arm/imx-common/hab.c
>> @@ -17,60 +17,45 @@
>>
>>  #define hab_rvt_report_event_p                                 \
>>  (                                                              \
>> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
>> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
>> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
>> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>>         ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
>> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
>> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
>> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
>
>This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is
>this on purpose? If so, then it means that there was something

Yeah. on purpose.

>unrelated to this patch that was wrong in this code for
>MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before
>this one. If not, then an is_mx6dl() macro should be introduced.

6solo and 6dl works the same. I do not plan to add a is_mx6dl here.
I can refine the commit log to note this in V2.

Stefano, do you have any comments on this?

Thanks,
Peng.

[U-Boot] [PATCH 03/13] imx-common: use simpler runtime cpu dection macros

[Benoît Thébaudeau]

Hi Peng,

On Fri, May 20, 2016 at 10:41 AM, Peng Fan <van.freenix@gmail.com> wrote:
> On Fri, May 20, 2016 at 01:02:10AM +0200, Beno?t Th?baudeau wrote:
>>On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote:
>>> Use simpler runtime cpu dection macros.
>>>
>>> Signed-off-by: Peng Fan <van.freenix@gmail.com>
>>> Cc: Stefano Babic <sbabic@denx.de>
>>> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com>
>>> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com>
>>> Cc: "Beno?t Th?baudeau" <benoit.thebaudeau.dev@gmail.com>
>>> ---
>>>  arch/arm/imx-common/hab.c      | 43 +++++++++++++-----------------------------
>>>  arch/arm/imx-common/init.c     |  5 ++---
>>>  arch/arm/imx-common/iomux-v3.c |  2 +-
>>>  arch/arm/imx-common/sata.c     |  2 +-
>>>  arch/arm/imx-common/timer.c    | 11 +++--------
>>>  5 files changed, 20 insertions(+), 43 deletions(-)
>>>
>>> diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c
>>> index 8bbcc22..a980688 100644
>>> --- a/arch/arm/imx-common/hab.c
>>> +++ b/arch/arm/imx-common/hab.c
>>> @@ -17,60 +17,45 @@
>>>
>>>  #define hab_rvt_report_event_p                                 \
>>>  (                                                              \
>>> -       ((is_cpu_type(MXC_CPU_MX6Q) ||                          \
>>> -         is_cpu_type(MXC_CPU_MX6D)) &&                         \
>>> -         (soc_rev() >= CHIP_REV_1_5)) ?                        \
>>> +       (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ?           \
>>>         ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) :  \
>>> -       (is_cpu_type(MXC_CPU_MX6DL) &&                          \
>>> -        (soc_rev() >= CHIP_REV_1_2)) ?                         \
>>> +       (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ?          \
>>
>>This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is
>>this on purpose? If so, then it means that there was something
>
> Yeah. on purpose.
>
>>unrelated to this patch that was wrong in this code for
>>MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before
>>this one. If not, then an is_mx6dl() macro should be introduced.
>
> 6solo and 6dl works the same. I do not plan to add a is_mx6dl here.
> I can refine the commit log to note this in V2.

Then you can indeed either mention this in the commit message, or add
a patch fixing 6solo support before this one.

Best regards,
Beno?t