[U-Boot] [PATCH] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address

[Chin Liang See <clsee@altera.com>]

Hi Marek,

On Thu, 2016-08-04 at 07:34 +0200, Marek Vasut wrote:
> On 08/03/2016 05:17 PM, Chin Liang See wrote:
> > Add base address header file for Stratix10 SoC
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> 
> Applied to the 01-arria10 branch , since this patch is useless in
> mainline as-is .

Cool and thanks. This is the patch for S10 SOCVP and I am validating my
development code now. 

Can we split this as another branch? Once its working with S10 SOCVP,
this shall be part of mainline. 

> 
> btw do you ever plan to finish the Arria10 support in mainline ?
> 

Definitely and getting Ley Foon's help for this.

Thanks
Chin Liang

> > ---
> >  arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 48
> > ++++++++++++++++++++++
> >  1 file changed, 48 insertions(+)
> >  create mode 100755 arch/arm/mach
> > -socfpga/include/mach/base_addr_s10.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > new file mode 100755
> > index 0000000..411518d
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
> > @@ -0,0 +1,48 @@
> > +/*
> > + * Copyright (C) 2016, Intel Corporation
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0
> > + */
> > +
> > +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
> > +#define _SOCFPGA_S10_BASE_HARDWARE_H_
> > +
> > +#define SOCFPGA_SMMU_ADDRESS			0xfa000000
> > +#define SOCFPGA_EMAC0_ADDRESS			0xff800000
> > +#define SOCFPGA_EMAC1_ADDRESS			0xff802000
> > +#define SOCFPGA_EMAC2_ADDRESS			0xff804000
> > +#define SOCFPGA_SDMMC_ADDRESS			0xff808000
> > +#define SOCFPGA_USB0_ADDRESS			0xffb00000
> > +#define SOCFPGA_USB1_ADDRESS			0xffb40000
> > +#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
> > +#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
> > +#define SOCFPGA_UART0_ADDRESS			0xffc02000
> > +#define SOCFPGA_UART1_ADDRESS			0xffc02100
> > +#define SOCFPGA_I2C0_ADDRESS			0xffc02800
> > +#define SOCFPGA_I2C1_ADDRESS			0xffc02900
> > +#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
> > +#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
> > +#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
> > +#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
> > +#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
> > +#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
> > +#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
> > +#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
> > +#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00100
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00300
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00400
> > +#define SOCFPGA_L4WD0_ADDRESS			0xffd00500
> > +#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
> > +#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
> > +#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
> > +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
> > +#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
> > +#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
> > +#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
> > +#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
> > +#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
> > +#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
> > +#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
> > +
> > +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
> > 
> 
>