From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Mon, 22 Aug 2016 22:18:24 +0800
Subject: [U-Boot] [PATCH v2 1/2] ARM: Move SYS_CACHELINE_SIZE over to
	Kconfig
In-Reply-To: <20160822133902.GC5342@bill-the-cat>
References: <1471868538-21965-1-git-send-email-trini@konsulko.com>
 <1471872244.1873.5.camel@altera.com> <20160822133902.GC5342@bill-the-cat>
Message-ID: <1471875504.2574.6.camel@altera.com>
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To: u-boot@lists.denx.de

On Mon, 2016-08-22 at 09:39 -0400, Tom Rini wrote:
> On Mon, Aug 22, 2016 at 09:24:04PM +0800, Chin Liang See wrote:
> > Hi Tom,
> > 
> > On Mon, 2016-08-22 at 08:22 -0400, Tom Rini wrote:
> > > This series moves the CONFIG_SYS_CACHELINE_SIZE.  First, in
> > > nearly
> > > all
> > > cases we are mirroring the values used by the Linux Kernel here. 
> > >  Also,
> > > so long as (and in this case, it is true) we implement flushes in
> > > hunks
> > > that are no larger than the smallest implementation (and given
> > > that
> > > we
> > > mirror the Linux Kernel, again we are fine) it is OK to align
> > > higher.
> > > The biggest changes here are that we always use 64 bytes for
> > > CPU_V7
> > > even
> > > if for example the underlying core is only 32 bytes (this mirrors
> > > Linux).  Second, we say ARM64 uses 64 bytes not 128 (as found in
> > > the
> > > Linux Kernel) as we do not need multi-platform support (to this
> > > degree)
> > > and only the Cavium ThunderX 88xx series has a use for such large
> > > alignment.
> > > 
> > > 
> > ...
> > 
> > >  arch/arm/Kconfig                                  | 27
> > 
> > > ... 
> > 
> > > 
> > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > index aef901c3f448..e6d4a2043854 100644
> > > --- a/arch/arm/Kconfig
> > > +++ b/arch/arm/Kconfig
> > > @@ -7,6 +7,7 @@ config SYS_ARCH
> > > 
> > 
> > ...
> > 
> > >  
> > >  config CPU_V7
> > >          bool
> > >          select HAS_VBAR
> > >          select HAS_THUMB2
> > > +	select SYS_CACHE_SHIFT_6
> > >  
> > 
> > CPU_V7 should use SYS_CACHE_SHIFT_5 which is 32 bytes cache lines.
> 
> No, some V7 are 32 and some are 64, for example Cortex-A8.
> 

Thanks Tom as you are right where its non standard across v7. In this
case, 64 will works for 32 case.

Acked-by: Chin Liang See <clsee@altera.com>

Thanks
Chin Liang

p/s: Reduced the mailing list as earlier email intention is to check
whether my earlier statement might not true in certain SoCs :)