From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Tue, 6 Sep 2016 13:14:38 +0800
Subject: [U-Boot] [PATCH 04/11] arm: socfpga: clkmgr: Segregate the
 Clock Manager for Stratix 10
In-Reply-To: <60bb86ca-57e6-8142-09f9-b1736cdf8ca3@denx.de>
References: <1471878163-3598-1-git-send-email-clsee@altera.com>
 <1471878163-3598-5-git-send-email-clsee@altera.com>
 <60bb86ca-57e6-8142-09f9-b1736cdf8ca3@denx.de>
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On Mon, 2016-09-05 at 17:58 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the Clock Manager to support both GEN5 SoC and
> > Stratix 10 SoC.
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> >  arch/arm/mach-socfpga/clock_manager.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach
> > -socfpga/clock_manager.c
> > index aa71636..0d67b3c 100644
> > --- a/arch/arm/mach-socfpga/clock_manager.c
> > +++ b/arch/arm/mach-socfpga/clock_manager.c
> > @@ -10,6 +10,7 @@
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  static const struct socfpga_clock_manager *clock_manager_base =
> >  	(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
> >  
> > @@ -446,9 +447,11 @@ unsigned int cm_get_l4_sp_clk_hz(void)
> >  
> >  	return clock;
> >  }
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >  
> >  unsigned int cm_get_mmc_controller_clk_hz(void)
> >  {
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  	uint32_t reg, clock = 0;
> >  
> >  	/* identify the source of MMC clock */
> > @@ -475,8 +478,12 @@ unsigned int
> > cm_get_mmc_controller_clk_hz(void)
> >  	/* further divide by 4 as we have fixed divider at wrapper
> > */
> >  	clock /= 4;
> >  	return clock;
> > +#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
> > +	return 25000000;
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> >  }
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> >  unsigned int cm_get_qspi_controller_clk_hz(void)
> 
> Are you sure this won't cause build breakage ? I believe this is
> still
> used by the cadence qspi driver.

That is a good question. As for SOC Virtual Platform, we are not
enabling the QSPI controller.

Thanks
Chin Liang

> 
> >  {
> >  	uint32_t reg, clock = 0;
> > @@ -556,3 +563,4 @@ U_BOOT_CMD(
> >  	"display clocks",
> >  	""
> >  );
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > 
> 
>