From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Tue, 6 Sep 2016 13:44:37 +0800
Subject: [U-Boot] [PATCH 05/11] arm: socfpga: fpgamgr: Segregate the
 FPGA Manager for Stratix 10
In-Reply-To: <b4e8787c-354b-8f1f-1e7a-369034efda54@denx.de>
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 <b4e8787c-354b-8f1f-1e7a-369034efda54@denx.de>
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On Mon, 2016-09-05 at 18:00 +0200, Marek Vasut wrote:
> On 08/22/2016 05:02 PM, Chin Liang See wrote:
> > Segregate the FPGA Manager to support both GEN5 SoC and
> > Stratix 10 SoC.
> > 
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
> > Cc: Ley Foon Tan <lftan@altera.com>
> > ---
> >  arch/arm/mach-socfpga/fpga_manager.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/arch/arm/mach-socfpga/fpga_manager.c b/arch/arm/mach
> > -socfpga/fpga_manager.c
> > index 43fd2fe..a01e062 100644
> > --- a/arch/arm/mach-socfpga/fpga_manager.c
> > +++ b/arch/arm/mach-socfpga/fpga_manager.c
> > @@ -20,6 +20,8 @@ DECLARE_GLOBAL_DATA_PTR;
> >  /* Timeout count */
> >  #define FPGA_TIMEOUT_CNT		0x1000000
> >  
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +
> >  static struct socfpga_fpga_manager *fpgamgr_regs =
> >  	(struct socfpga_fpga_manager
> > *)SOCFPGA_FPGAMGRREGS_ADDRESS;
> >  
> > @@ -76,3 +78,5 @@ int fpgamgr_poll_fpga_ready(void)
> >  
> >  	return 0;
> >  }
> > +
> > +#endif /* CONFIG_TARGET_SOCFPGA_GEN5 */
> > 
> Did you just disable the whole file ? If so, then just don't compile
> it
> at all, just add conditional into the Makefile.
> 

Yes, I just realize that :) I shall fix the Makefile instead of this
patch.

Thanks
Chin Liang