From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Mon, 19 Sep 2016 18:12:40 +0800 Subject: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 In-Reply-To: References: <1473924446-29927-1-git-send-email-clsee@altera.com> Message-ID: <1474279960.29599.13.camel@altera.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote: > On 09/15/2016 09:27 AM, Chin Liang See wrote: > > Adding new handoff for SDRAM ctrcfg.extratime1 which is > > required for stabil LPDDR2 operation > > ... stable ... > > Isn't SoCDK using DDR3 DRAM ? Yah, you are right where we won't need this patch and others except #1 one. Should I send v2 which only have first patch? Thanks Chin Liang > > > Signed-off-by: Chin Liang See > > --- > > board/altera/arria5-socdk/qts/sdram_config.h | 3 +++ > > board/altera/cyclone5-socdk/qts/sdram_config.h | 3 +++ > > 2 files changed, 6 insertions(+) > > > > diff --git a/board/altera/arria5-socdk/qts/sdram_config.h > > b/board/altera/arria5-socdk/qts/sdram_config.h > > index e9fe60f..8964637 100644 > > --- a/board/altera/arria5-socdk/qts/sdram_config.h > > +++ b/board/altera/arria5-socdk/qts/sdram_config.h > > @@ -49,6 +49,9 @@ > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP > > 4 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT > > 512 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C > > HIP 2 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST > > 0 > > diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h > > b/board/altera/cyclone5-socdk/qts/sdram_config.h > > index 37c1476..1bc6f6f 100644 > > --- a/board/altera/cyclone5-socdk/qts/sdram_config.h > > +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h > > @@ -49,6 +49,9 @@ > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT > > 3 > > #define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT > > 512 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 > > +#define > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_C > > HIP 2 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE > > 0 > > #define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST > > 0 > > > >