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From: Chin Liang See <clsee@altera.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1
Date: Tue, 20 Sep 2016 13:37:56 +0800	[thread overview]
Message-ID: <1474349876.2525.0.camel@altera.com> (raw)
In-Reply-To: <7c740409-a073-bb72-19ea-e6d9ae7a6e35@denx.de>

On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > > > required for stabil LPDDR2 operation
> > > 
> > > ... stable ...
> > > 
> > > Isn't SoCDK using DDR3 DRAM ?
> > 
> > Yah, you are right where we won't need this patch and others except
> > #1
> > one. Should I send v2 which only have first patch?
> 
> Then should this register be set to zero on SoCDK ?

Not required as the default value is zero.

Thanks
Chin Liang

> 
> 

  reply	other threads:[~2016-09-20  5:37 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-15  7:27 [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM ctrlcfg.extratime1 Chin Liang See
2016-09-19 14:24 ` Marek Vasut
2016-09-19 10:12   ` Chin Liang See
2016-09-19 18:52     ` Marek Vasut
2016-09-20  5:37       ` Chin Liang See [this message]
2016-09-20  7:52         ` Marek Vasut
2016-09-20  9:13           ` Chin Liang See
2016-09-21  1:19             ` Marek Vasut

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