From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chin Liang See <clsee@altera.com>
Date: Tue, 20 Sep 2016 13:37:56 +0800
Subject: [U-Boot] [PATCH 2/9] arm: socfpga: Adding handoff for SDRAM
 ctrlcfg.extratime1
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On Mon, 2016-09-19 at 20:52 +0200, Marek Vasut wrote:
> On 09/19/2016 12:12 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:24 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:27 AM, Chin Liang See wrote:
> > > > Adding new handoff for SDRAM ctrcfg.extratime1 which is
> > > > required for stabil LPDDR2 operation
> > > 
> > > ... stable ...
> > > 
> > > Isn't SoCDK using DDR3 DRAM ?
> > 
> > Yah, you are right where we won't need this patch and others except
> > #1
> > one. Should I send v2 which only have first patch?
> 
> Then should this register be set to zero on SoCDK ?

Not required as the default value is zero.

Thanks
Chin Liang

> 
>