* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
@ 2016-09-15 7:26 Chin Liang See
2016-09-19 14:22 ` Marek Vasut
0 siblings, 1 reply; 7+ messages in thread
From: Chin Liang See @ 2016-09-15 7:26 UTC (permalink / raw)
To: u-boot
To enable configuration of sdr.ctrlcfg.extratime1 register which enable
extra clocks for read to write command timing. This is critical to
ensure successful LPDDR2 interface
Signed-off-by: Chin Liang See <clsee@altera.com>
---
arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
arch/arm/mach-socfpga/qts-filter.sh | 2 +-
arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
drivers/ddr/altera/sdram.c | 3 +++
4 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
index f12bb84..b11228f 100644
--- a/arch/arm/mach-socfpga/include/mach/sdram.h
+++ b/arch/arm/mach-socfpga/include/mach/sdram.h
@@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
u32 dram_timing4; /* 0x10 */
u32 lowpwr_timing;
u32 dram_odt;
- u32 __padding0[4];
+ u32 extratime1;
+ u32 __padding0[3];
u32 dram_addrw; /* 0x2c */
u32 dram_if_width; /* 0x30 */
u32 dram_dev_width;
@@ -88,6 +89,7 @@ struct socfpga_sdram_config {
u32 dram_timing4;
u32 lowpwr_timing;
u32 dram_odt;
+ u32 extratime1;
u32 dram_addrw;
u32 dram_if_width;
u32 dram_dev_width;
@@ -427,6 +429,10 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \
/* Field instance: sdr::ctrlgrp::dramsts */
#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008
#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004
+/* Register template: sdr::ctrlgrp::extratime1 */
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24
+#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28
/* SDRAM width macro for configuration with ECC */
#define SDRAM_WIDTH_32BIT_WITH_ECC 40
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh
index 050d6ba..1148a71 100755
--- a/arch/arm/mach-socfpga/qts-filter.sh
+++ b/arch/arm/mach-socfpga/qts-filter.sh
@@ -119,7 +119,7 @@ EOF
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
- egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!
NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_A!
CTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_RE!
FRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_D
ATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL)[[:space:]]"
+ egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CO!
NFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP!
|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_POR
TCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_A!
CTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_RE!
FRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_D
ATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_T!
O_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}
#
diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
index 31cc7de..d72f5e1 100644
--- a/arch/arm/mach-socfpga/wrap_sdram_config.c
+++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
@@ -81,6 +81,15 @@ static const struct socfpga_sdram_config sdram_config = {
SDR_CTRLGRP_DRAMODT_READ_LSB) |
(CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
SDR_CTRLGRP_DRAMODT_WRITE_LSB),
+#ifdef CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
+ .extratime1 =
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
+(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
+ SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
+#endif
.dram_addrw =
(CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 7e4606d..e74c5b0 100644
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+
+ debug("Configuring EXTRATIME1\n");
+ writel(cfg->extratime1, &sdr_ctrl->extratime1);
}
/**
--
2.2.2
^ permalink raw reply related [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-15 7:26 [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters Chin Liang See
@ 2016-09-19 14:22 ` Marek Vasut
2016-09-19 10:11 ` Chin Liang See
0 siblings, 1 reply; 7+ messages in thread
From: Marek Vasut @ 2016-09-19 14:22 UTC (permalink / raw)
To: u-boot
On 09/15/2016 09:26 AM, Chin Liang See wrote:
> To enable configuration of sdr.ctrlcfg.extratime1 register which enable
> extra clocks for read to write command timing. This is critical to
> ensure successful LPDDR2 interface
>
> Signed-off-by: Chin Liang See <clsee@altera.com>
> ---
> arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
> arch/arm/mach-socfpga/qts-filter.sh | 2 +-
> arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
> drivers/ddr/altera/sdram.c | 3 +++
> 4 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h
> index f12bb84..b11228f 100644
> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
> u32 dram_timing4; /* 0x10 */
> u32 lowpwr_timing;
> u32 dram_odt;
> - u32 __padding0[4];
> + u32 extratime1;
> + u32 __padding0[3];
> u32 dram_addrw; /* 0x2c */
> u32 dram_if_width; /* 0x30 */
> u32 dram_dev_width;
> @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
> u32 dram_timing4;
> u32 lowpwr_timing;
> u32 dram_odt;
> + u32 extratime1;
> u32 dram_addrw;
> u32 dram_if_width;
> u32 dram_dev_width;
This seems to be changing the DRAM register layout, is this really
correct and was this really tested on AV SoCDK ?
[...]
> diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c
> index 31cc7de..d72f5e1 100644
> --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config sdram_config = {
> SDR_CTRLGRP_DRAMODT_READ_LSB) |
> (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> +#ifdef CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
How come this is not always defined for all boards ?
> + .extratime1 =
> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR <<
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) |
> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC <<
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) |
> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP <<
> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
> +#endif
> .dram_addrw =
> (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
> diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
> index 7e4606d..e74c5b0 100644
> --- a/drivers/ddr/altera/sdram.c
> +++ b/drivers/ddr/altera/sdram.c
> @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct socfpga_sdram_config *cfg)
>
> debug("Configuring DRAMODT\n");
> writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
> +
> + debug("Configuring EXTRATIME1\n");
> + writel(cfg->extratime1, &sdr_ctrl->extratime1);
> }
>
> /**
>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-19 14:22 ` Marek Vasut
@ 2016-09-19 10:11 ` Chin Liang See
2016-09-19 18:54 ` Marek Vasut
0 siblings, 1 reply; 7+ messages in thread
From: Chin Liang See @ 2016-09-19 10:11 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > To enable configuration of sdr.ctrlcfg.extratime1 register which
> > enable
> > extra clocks for read to write command timing. This is critical to
> > ensure successful LPDDR2 interface
> >
> > Signed-off-by: Chin Liang See <clsee@altera.com>
> > ---
> > arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
> > arch/arm/mach-socfpga/qts-filter.sh | 2 +-
> > arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
> > drivers/ddr/altera/sdram.c | 3 +++
> > 4 files changed, 20 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > index f12bb84..b11228f 100644
> > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
> > u32 dram_timing4; /* 0x10 */
> > u32 lowpwr_timing;
> > u32 dram_odt;
> > - u32 __padding0[4];
> > + u32 extratime1;
> > + u32 __padding0[3];
> > u32 dram_addrw; /* 0x2c */
> > u32 dram_if_width; /* 0x30 */
> > u32 dram_dev_width;
> > @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
> > u32 dram_timing4;
> > u32 lowpwr_timing;
> > u32 dram_odt;
> > + u32 extratime1;
> > u32 dram_addrw;
> > u32 dram_if_width;
> > u32 dram_dev_width;
>
> This seems to be changing the DRAM register layout, is this really
> correct and was this really tested on AV SoCDK ?
Previously its treated unused register as default value is good enough.
But this not true anymore for LPDDR2 and we are exposing extratime1
register.
While for testing, I tested both CV and AV SoCDK few times as I also
worried even they are using DDR3 instead LPDDR2.
>
> [...]
>
> > diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > index 31cc7de..d72f5e1 100644
> > --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
> > sdram_config = {
> > SDR_CTRLGRP_DRAMODT_READ_LSB)
> > |
> > (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > +#ifdef
> > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
>
> How come this is not always defined for all boards ?
This is to ensure it still works if users are using older SOCEDS
instead of SOCEDS 16.1. Besides that, this is only applicable for
LPDDR2. With that, patches #2 to #9 are not needed.
Thanks
Chin Liang
>
> > + .extratime1 =
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
> > _WR <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)
> > |
> > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
> > _WR_BC <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)
> > |
> > +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF
> > _CHIP <<
> > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
> > +#endif
> > .dram_addrw =
> > (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> > SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)
> > |
> > diff --git a/drivers/ddr/altera/sdram.c
> > b/drivers/ddr/altera/sdram.c
> > index 7e4606d..e74c5b0 100644
> > --- a/drivers/ddr/altera/sdram.c
> > +++ b/drivers/ddr/altera/sdram.c
> > @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct
> > socfpga_sdram_config *cfg)
> >
> > debug("Configuring DRAMODT\n");
> > writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
> > +
> > + debug("Configuring EXTRATIME1\n");
> > + writel(cfg->extratime1, &sdr_ctrl->extratime1);
> > }
> >
> > /**
> >
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-19 10:11 ` Chin Liang See
@ 2016-09-19 18:54 ` Marek Vasut
2016-09-19 18:54 ` Marek Vasut
2016-09-20 5:50 ` Chin Liang See
0 siblings, 2 replies; 7+ messages in thread
From: Marek Vasut @ 2016-09-19 18:54 UTC (permalink / raw)
To: u-boot
On 09/19/2016 12:11 PM, Chin Liang See wrote:
> On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
>> On 09/15/2016 09:26 AM, Chin Liang See wrote:
>>> To enable configuration of sdr.ctrlcfg.extratime1 register which
>>> enable
>>> extra clocks for read to write command timing. This is critical to
>>> ensure successful LPDDR2 interface
>>>
>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>> ---
>>> arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
>>> arch/arm/mach-socfpga/qts-filter.sh | 2 +-
>>> arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
>>> drivers/ddr/altera/sdram.c | 3 +++
>>> 4 files changed, 20 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> index f12bb84..b11228f 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>> @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
>>> u32 dram_timing4; /* 0x10 */
>>> u32 lowpwr_timing;
>>> u32 dram_odt;
>>> - u32 __padding0[4];
>>> + u32 extratime1;
>>> + u32 __padding0[3];
>>> u32 dram_addrw; /* 0x2c */
>>> u32 dram_if_width; /* 0x30 */
>>> u32 dram_dev_width;
>>> @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
>>> u32 dram_timing4;
>>> u32 lowpwr_timing;
>>> u32 dram_odt;
>>> + u32 extratime1;
>>> u32 dram_addrw;
>>> u32 dram_if_width;
>>> u32 dram_dev_width;
>>
>> This seems to be changing the DRAM register layout, is this really
>> correct and was this really tested on AV SoCDK ?
>
> Previously its treated unused register as default value is good enough.
> But this not true anymore for LPDDR2 and we are exposing extratime1
> register.
I mean the later one , which adds an entry and moves the other registers
by 4 bytes.
> While for testing, I tested both CV and AV SoCDK few times as I also
> worried even they are using DDR3 instead LPDDR2.
Yes, they do, it's in the documentation ;-)
>>
>> [...]
>>
>>> diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
>>> b/arch/arm/mach-socfpga/wrap_sdram_config.c
>>> index 31cc7de..d72f5e1 100644
>>> --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
>>> +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
>>> @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
>>> sdram_config = {
>>> SDR_CTRLGRP_DRAMODT_READ_LSB)
>>> |
>>> (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>>> SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>>> +#ifdef
>>> CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
>>
>> How come this is not always defined for all boards ?
>
> This is to ensure it still works if users are using older SOCEDS
> instead of SOCEDS 16.1. Besides that, this is only applicable for
> LPDDR2. With that, patches #2 to #9 are not needed.
>
> Thanks
> Chin Liang
>
>>
>>> + .extratime1 =
>>> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
>>> _WR <<
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)
>>> |
>>> + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO
>>> _WR_BC <<
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB)
>>> |
>>> +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF
>>> _CHIP <<
>>> + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB),
>>> +#endif
>>> .dram_addrw =
>>> (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
>>> SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)
>>> |
>>> diff --git a/drivers/ddr/altera/sdram.c
>>> b/drivers/ddr/altera/sdram.c
>>> index 7e4606d..e74c5b0 100644
>>> --- a/drivers/ddr/altera/sdram.c
>>> +++ b/drivers/ddr/altera/sdram.c
>>> @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct
>>> socfpga_sdram_config *cfg)
>>>
>>> debug("Configuring DRAMODT\n");
>>> writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
>>> +
>>> + debug("Configuring EXTRATIME1\n");
>>> + writel(cfg->extratime1, &sdr_ctrl->extratime1);
>>> }
>>>
>>> /**
>>>
>>
>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-19 18:54 ` Marek Vasut
@ 2016-09-19 18:54 ` Marek Vasut
2016-09-20 5:50 ` Chin Liang See
1 sibling, 0 replies; 7+ messages in thread
From: Marek Vasut @ 2016-09-19 18:54 UTC (permalink / raw)
To: u-boot
On 09/19/2016 08:54 PM, Marek Vasut wrote:
> On 09/19/2016 12:11 PM, Chin Liang See wrote:
>> On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
>>> On 09/15/2016 09:26 AM, Chin Liang See wrote:
>>>> To enable configuration of sdr.ctrlcfg.extratime1 register which
>>>> enable
>>>> extra clocks for read to write command timing. This is critical to
>>>> ensure successful LPDDR2 interface
>>>>
>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>> ---
>>>> arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
>>>> arch/arm/mach-socfpga/qts-filter.sh | 2 +-
>>>> arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
>>>> drivers/ddr/altera/sdram.c | 3 +++
>>>> 4 files changed, 20 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>>> index f12bb84..b11228f 100644
>>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>>> @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
>>>> u32 dram_timing4; /* 0x10 */
>>>> u32 lowpwr_timing;
>>>> u32 dram_odt;
>>>> - u32 __padding0[4];
>>>> + u32 extratime1;
>>>> + u32 __padding0[3];
>>>> u32 dram_addrw; /* 0x2c */
>>>> u32 dram_if_width; /* 0x30 */
>>>> u32 dram_dev_width;
>>>> @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
>>>> u32 dram_timing4;
>>>> u32 lowpwr_timing;
>>>> u32 dram_odt;
>>>> + u32 extratime1;
>>>> u32 dram_addrw;
>>>> u32 dram_if_width;
>>>> u32 dram_dev_width;
>>>
>>> This seems to be changing the DRAM register layout, is this really
>>> correct and was this really tested on AV SoCDK ?
>>
>> Previously its treated unused register as default value is good enough.
>> But this not true anymore for LPDDR2 and we are exposing extratime1
>> register.
>
> I mean the later one , which adds an entry and moves the other registers
> by 4 bytes.
>
>> While for testing, I tested both CV and AV SoCDK few times as I also
>> worried even they are using DDR3 instead LPDDR2.
>
> Yes, they do, it's in the documentation ;-)
>
>>>
>>> [...]
>>>
>>>> diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
>>>> b/arch/arm/mach-socfpga/wrap_sdram_config.c
>>>> index 31cc7de..d72f5e1 100644
>>>> --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
>>>> +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
>>>> @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
>>>> sdram_config = {
>>>> SDR_CTRLGRP_DRAMODT_READ_LSB)
>>>> |
>>>> (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
>>>> SDR_CTRLGRP_DRAMODT_WRITE_LSB),
>>>> +#ifdef
>>>> CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
>>>
>>> How come this is not always defined for all boards ?
>>
>> This is to ensure it still works if users are using older SOCEDS
>> instead of SOCEDS 16.1. Besides that, this is only applicable for
>> LPDDR2. With that, patches #2 to #9 are not needed.
We don't support old crap :)
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-19 18:54 ` Marek Vasut
2016-09-19 18:54 ` Marek Vasut
@ 2016-09-20 5:50 ` Chin Liang See
2016-09-21 1:18 ` Marek Vasut
1 sibling, 1 reply; 7+ messages in thread
From: Chin Liang See @ 2016-09-20 5:50 UTC (permalink / raw)
To: u-boot
On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote:
> On 09/19/2016 12:11 PM, Chin Liang See wrote:
> > On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
> > > On 09/15/2016 09:26 AM, Chin Liang See wrote:
> > > > To enable configuration of sdr.ctrlcfg.extratime1 register
> > > > which
> > > > enable
> > > > extra clocks for read to write command timing. This is critical
> > > > to
> > > > ensure successful LPDDR2 interface
> > > >
> > > > Signed-off-by: Chin Liang See <clsee@altera.com>
> > > > ---
> > > > arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
> > > > arch/arm/mach-socfpga/qts-filter.sh | 2 +-
> > > > arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
> > > > drivers/ddr/altera/sdram.c | 3 +++
> > > > 4 files changed, 20 insertions(+), 2 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index f12bb84..b11228f 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
> > > > u32 dram_timing4; /* 0x10 */
> > > > u32 lowpwr_timing;
> > > > u32 dram_odt;
> > > > - u32 __padding0[4];
> > > > + u32 extratime1;
> > > > + u32 __padding0[3];
> > > > u32 dram_addrw; /* 0x2c */
> > > > u32 dram_if_width; /* 0x30 */
> > > > u32 dram_dev_width;
> > > > @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
> > > > u32 dram_timing4;
> > > > u32 lowpwr_timing;
> > > > u32 dram_odt;
> > > > + u32 extratime1;
> > > > u32 dram_addrw;
> > > > u32 dram_if_width;
> > > > u32 dram_dev_width;
> > >
> > > This seems to be changing the DRAM register layout, is this
> > > really
> > > correct and was this really tested on AV SoCDK ?
> >
> > Previously its treated unused register as default value is good
> > enough.
> > But this not true anymore for LPDDR2 and we are exposing extratime1
> > register.
>
> I mean the later one , which adds an entry and moves the other
> registers
> by 4 bytes.
Oh you referring to socfpga_sdram_config. That structure is used to
store the handoff value. The address of register is actually pointed by
structure socfpga_sdr_ctrl.
>
> > While for testing, I tested both CV and AV SoCDK few times as I
> > also
> > worried even they are using DDR3 instead LPDDR2.
>
> Yes, they do, it's in the documentation ;-)
Oh actually I meant that this patch should not impact existing boards
which are using DDR3.
Thanks
Chin Liang
>
> > >
> > > [...]
> > >
> > > > diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > index 31cc7de..d72f5e1 100644
> > > > --- a/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c
> > > > @@ -81,6 +81,15 @@ static const struct socfpga_sdram_config
> > > > sdram_config = {
> > > > SDR_CTRLGRP_DRAMODT_READ_LSB)
> > > > |
> > > > (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE <<
> > > > SDR_CTRLGRP_DRAMODT_WRITE_LSB),
> > > > +#ifdef
> > > > CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR
> > >
> > > How come this is not always defined for all boards ?
> >
> > This is to ensure it still works if users are using older SOCEDS
> > instead of SOCEDS 16.1. Besides that, this is only applicable for
> > LPDDR2. With that, patches #2 to #9 are not needed.
> >
> > Thanks
> > Chin Liang
> >
> > >
> > > > + .extratime1 =
> > > > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_R
> > > > D_TO
> > > > _WR <<
> > > > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB)
> > > > |
> > > > + (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_R
> > > > D_TO
> > > > _WR_BC <<
> > > > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB
> > > > )
> > > > |
> > > > +(CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_
> > > > DIFF
> > > > _CHIP <<
> > > > + SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_L
> > > > SB),
> > > > +#endif
> > > > .dram_addrw =
> > > > (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
> > > > SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB)
> > > >
> > > > >
> > > > diff --git a/drivers/ddr/altera/sdram.c
> > > > b/drivers/ddr/altera/sdram.c
> > > > index 7e4606d..e74c5b0 100644
> > > > --- a/drivers/ddr/altera/sdram.c
> > > > +++ b/drivers/ddr/altera/sdram.c
> > > > @@ -418,6 +418,9 @@ static void sdr_load_regs(const struct
> > > > socfpga_sdram_config *cfg)
> > > >
> > > > debug("Configuring DRAMODT\n");
> > > > writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
> > > > +
> > > > + debug("Configuring EXTRATIME1\n");
> > > > + writel(cfg->extratime1, &sdr_ctrl->extratime1);
> > > > }
> > > >
> > > > /**
> > > >
> > >
> > >
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread* [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters
2016-09-20 5:50 ` Chin Liang See
@ 2016-09-21 1:18 ` Marek Vasut
0 siblings, 0 replies; 7+ messages in thread
From: Marek Vasut @ 2016-09-21 1:18 UTC (permalink / raw)
To: u-boot
On 09/20/2016 07:50 AM, Chin Liang See wrote:
> On Mon, 2016-09-19 at 20:54 +0200, Marek Vasut wrote:
>> On 09/19/2016 12:11 PM, Chin Liang See wrote:
>>> On Mon, 2016-09-19 at 16:22 +0200, Marek Vasut wrote:
>>>> On 09/15/2016 09:26 AM, Chin Liang See wrote:
>>>>> To enable configuration of sdr.ctrlcfg.extratime1 register
>>>>> which
>>>>> enable
>>>>> extra clocks for read to write command timing. This is critical
>>>>> to
>>>>> ensure successful LPDDR2 interface
>>>>>
>>>>> Signed-off-by: Chin Liang See <clsee@altera.com>
>>>>> ---
>>>>> arch/arm/mach-socfpga/include/mach/sdram.h | 8 +++++++-
>>>>> arch/arm/mach-socfpga/qts-filter.sh | 2 +-
>>>>> arch/arm/mach-socfpga/wrap_sdram_config.c | 9 +++++++++
>>>>> drivers/ddr/altera/sdram.c | 3 +++
>>>>> 4 files changed, 20 insertions(+), 2 deletions(-)
>>>>>
>>>>> diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
>>>>> b/arch/arm/mach-socfpga/include/mach/sdram.h
>>>>> index f12bb84..b11228f 100644
>>>>> --- a/arch/arm/mach-socfpga/include/mach/sdram.h
>>>>> +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
>>>>> @@ -30,7 +30,8 @@ struct socfpga_sdr_ctrl {
>>>>> u32 dram_timing4; /* 0x10 */
>>>>> u32 lowpwr_timing;
>>>>> u32 dram_odt;
>>>>> - u32 __padding0[4];
>>>>> + u32 extratime1;
>>>>> + u32 __padding0[3];
>>>>> u32 dram_addrw; /* 0x2c */
>>>>> u32 dram_if_width; /* 0x30 */
>>>>> u32 dram_dev_width;
>>>>> @@ -88,6 +89,7 @@ struct socfpga_sdram_config {
>>>>> u32 dram_timing4;
>>>>> u32 lowpwr_timing;
>>>>> u32 dram_odt;
>>>>> + u32 extratime1;
>>>>> u32 dram_addrw;
>>>>> u32 dram_if_width;
>>>>> u32 dram_dev_width;
>>>>
>>>> This seems to be changing the DRAM register layout, is this
>>>> really
>>>> correct and was this really tested on AV SoCDK ?
>>>
>>> Previously its treated unused register as default value is good
>>> enough.
>>> But this not true anymore for LPDDR2 and we are exposing extratime1
>>> register.
>>
>> I mean the later one , which adds an entry and moves the other
>> registers
>> by 4 bytes.
>
> Oh you referring to socfpga_sdram_config. That structure is used to
> store the handoff value. The address of register is actually pointed by
> structure socfpga_sdr_ctrl.
Ah, missed that one, sorry.
[...]
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2016-09-21 1:18 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-09-15 7:26 [U-Boot] [PATCH 1/9] ddr: altera: Configuring SDRAM extra cycles timing parameters Chin Liang See
2016-09-19 14:22 ` Marek Vasut
2016-09-19 10:11 ` Chin Liang See
2016-09-19 18:54 ` Marek Vasut
2016-09-19 18:54 ` Marek Vasut
2016-09-20 5:50 ` Chin Liang See
2016-09-21 1:18 ` Marek Vasut
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