From: Jagan Teki <jteki@openedev.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 21/23] imx6: icorem6: Add NAND support
Date: Mon, 24 Oct 2016 17:27:40 +0530 [thread overview]
Message-ID: <1477310262-17841-22-git-send-email-jteki@openedev.com> (raw)
In-Reply-To: <1477310262-17841-1-git-send-email-jteki@openedev.com>
From: Jagan Teki <jagan@amarulasolutions.com>
Add NAND support for Engicam i.CoreM6 qdl board.
Boot Log:
--------
U-Boot SPL 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43)
Trying to boot from NAND
NAND : 512 MiB
U-Boot 2016.09-rc2-30755-gd3dc581-dirty (Sep 28 2016 - 23:00:43 +0530)
CPU: Freescale i.MX6SOLO rev1.3 at 792MHz
CPU: Industrial temperature grade (-40C to 105C) at 55C
Reset cause: WDOG
Model: Engicam i.CoreM6 DualLite/Solo Starter Kit
DRAM: 256 MiB
NAND: 512 MiB
MMC: FSL_SDHC: 0
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
icorem6qdl>
Cc: Scott Wood <oss@buserror.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
board/engicam/icorem6/icorem6.c | 63 ++++++++++++++++++++++++++++++++++++
configs/imx6qdl_icore_nand_defconfig | 37 +++++++++++++++++++++
include/configs/imx6qdl_icore.h | 25 +++++++++++++-
3 files changed, 124 insertions(+), 1 deletion(-)
create mode 100644 configs/imx6qdl_icore_nand_defconfig
diff --git a/board/engicam/icorem6/icorem6.c b/board/engicam/icorem6/icorem6.c
index a370c8b..c152007 100644
--- a/board/engicam/icorem6/icorem6.c
+++ b/board/engicam/icorem6/icorem6.c
@@ -101,6 +101,66 @@ int board_eth_init(bd_t *bis)
}
#endif
+#ifdef CONFIG_NAND_MXS
+
+#define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+#define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
+ PAD_CTL_SRE_FAST)
+#define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
+
+iomux_v3_cfg_t gpmi_pads[] = {
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
+};
+
+static void setup_gpmi_nand(void)
+{
+ struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ /* config gpmi nand iomux */
+ SETUP_IOMUX_PADS(gpmi_pads);
+
+ /* gate ENFC_CLK_ROOT clock first,before clk source switch */
+ clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* config gpmi and bch clock to 100 MHz */
+ clrsetbits_le32(&mxc_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
+ MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
+ MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
+ MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
+
+ /* enable ENFC_CLK_ROOT clock */
+ setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+
+ /* enable gpmi and bch clock gating */
+ setbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
+ MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
+
+ /* enable apbh clock gating */
+ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
+}
+#endif
+
int board_early_init_f(void)
{
SETUP_IOMUX_PADS(uart4_pads);
@@ -113,6 +173,9 @@ int board_init(void)
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+#ifdef CONFIG_NAND_MXS
+ setup_gpmi_nand();
+#endif
return 0;
}
diff --git a/configs/imx6qdl_icore_nand_defconfig b/configs/imx6qdl_icore_nand_defconfig
new file mode 100644
index 0000000..8ac3099
--- /dev/null
+++ b/configs/imx6qdl_icore_nand_defconfig
@@ -0,0 +1,37 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_MX6Q_ICORE=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,ENV_IS_IN_NAND"
+CONFIG_DEFAULT_FDT_FILE="imx6dl-icore.dtb"
+CONFIG_DEFAULT_DEVICE_TREE="imx6dl-icore"
+CONFIG_SYS_PROMPT="icorem6qdl> "
+CONFIG_SPL=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTO_COMPLETE=y
+CONFIG_SYS_MAXARGS=32
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FEC_MXC=y
+CONFIG_MXC_UART=y
+CONFIG_NAND_MXS=y
+CONFIG_NETDEVICES=y
+CONFIG_IMX_THERMAL=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX6=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SPL_DMA_SUPPORT=y
diff --git a/include/configs/imx6qdl_icore.h b/include/configs/imx6qdl_icore.h
index 6b58447..cd3aa43 100644
--- a/include/configs/imx6qdl_icore.h
+++ b/include/configs/imx6qdl_icore.h
@@ -27,6 +27,10 @@
/* Environment in MMC */
# if defined(CONFIG_ENV_IS_IN_MMC)
# define CONFIG_ENV_OFFSET 0x100000
+/* Environment in NAND */
+# elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET 0x400000
+# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
# endif
#endif
@@ -111,6 +115,20 @@
# define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#endif
+/* NAND */
+#ifdef CONFIG_NAND_MXS
+# define CONFIG_SYS_MAX_NAND_DEVICE 1
+# define CONFIG_SYS_NAND_BASE 0x40000000
+# define CONFIG_SYS_NAND_5_ADDR_CYCLE
+# define CONFIG_SYS_NAND_ONFI_DETECTION
+# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
+# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000
+
+# define CONFIG_APBH_DMA
+# define CONFIG_APBH_DMA_BURST
+# define CONFIG_APBH_DMA_BURST8
+#endif
+
/* Ethernet */
#ifdef CONFIG_FEC_MXC
# define IMX_FEC_BASE ENET_BASE_ADDR
@@ -125,7 +143,12 @@
/* SPL */
#ifdef CONFIG_SPL
-# define CONFIG_SPL_MMC_SUPPORT
+# ifdef CONFIG_NAND_MXS
+# define CONFIG_SPL_NAND_SUPPORT
+# else
+# define CONFIG_SPL_MMC_SUPPORT
+# endif
+
# include "imx6_spl.h"
# ifdef CONFIG_SPL_BUILD
# undef CONFIG_DM_GPIO
--
2.7.4
next prev parent reply other threads:[~2016-10-24 11:57 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-24 11:57 [U-Boot] [PATCH v8 00/23] imx6: Add Engicam i.CoreM6 QDL support Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 01/23] serial: Kconfig: Add MXC_UART entry Jagan Teki
2016-10-26 17:14 ` Markus Niebel
2016-10-26 17:44 ` Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 02/23] thermal: Kconfig: Add IMX_THERMAL entry Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 03/23] config: Move CONFIG_DEFAULT_FDT_FILE to defconfigs Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 04/23] arm: imx: Add Engicam i.CoreM6 QDL Starter Kit initial support Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 05/23] net: Kconfig: Add FEC_MXC entry Jagan Teki
2016-10-26 17:16 ` Markus Niebel
2016-10-26 18:04 ` Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 06/23] imx6: icorem6: Add ENET support Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 07/23] imx: s/docs\/README.imximage/doc\/README.imximage/g Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 08/23] arm: dts: Add devicetree for i.MX6DL Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 09/23] arm: dts: Add devicetree for i.MX6DQL Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 10/23] arm: dts: imx6dl: Add pinctrl defines Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 11/23] dt-bindings: clock: imx6qdl: Add clock defines Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 12/23] arm: imx6q: Add devicetree support for Engicam i.CoreM6 DualLite/Solo Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 13/23] imx6q: icorem6: Enable pinctrl driver Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 14/23] configs: imx6qdl: Enable CONFIG_BLK if DM_MMC Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 15/23] configs: imx6qdl: Enable CONFIG_DM_MMC_OPS " Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 16/23] engicam: icorem6: Add DM_GPIO, DM_MMC support Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 17/23] arm: dts: Add devicetree for i.MX6Q Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 18/23] arm: dts: imx6q: Add pinctrl defines Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 19/23] arm: imx6q: Add devicetree support for Engicam i.CoreM6 Quad/Dual Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 20/23] mtd: nand: Kconfig: Add NAND_MXS entry Jagan Teki
2016-10-24 11:57 ` Jagan Teki [this message]
2016-10-24 11:57 ` [U-Boot] [PATCH v8 22/23] imx6: icorem6: Enable MTD device support Jagan Teki
2016-10-24 11:57 ` [U-Boot] [PATCH v8 23/23] imx6: icorem6: Add default mtd nand partition table Jagan Teki
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1477310262-17841-22-git-send-email-jteki@openedev.com \
--to=jteki@openedev.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox