[U-Boot] [PATCH V2 0/4] mx6: ddr: updates for dynamic DDR calibration

[Eric Nelson <eric@nelint.com>]

This set of patches updates the interface to the DDR calibration in 
preparation for the addition of a pseudo-board for calibration on
i.MX6.

The first patch fixes an ommission in the use of the DG_CMP_CYC flag
in register MPDGCTRL0.

The second patch cleans up the handling of bus widths by passing
the system configuration information to the calibration routines.

The third patch adds support for returning the calibration data
written to the MMDC registers.

The fourth patch adds a Kconfig selection to inclut the DDR calibration
routines.

Eric Nelson (4):
  mx6: ddr: allow 32 cycles for DQS gating calibration
  mx6: ddr: pass mx6_ddr_sysinfo to calibration routines
  mx6: ddr: add routine to return DDR calibration data
  ARM: mx6: ddr: use Kconfig for inclusion of DDR calibration routines

 arch/arm/cpu/armv7/mx6/Kconfig          |   5 ++
 arch/arm/cpu/armv7/mx6/ddr.c            | 131 +++++++++++++++++++++-----------
 arch/arm/include/asm/arch-mx6/mx6-ddr.h |   8 +-
 board/kosagi/novena/novena_spl.c        |   4 +-
 configs/novena_defconfig                |   1 +
 5 files changed, 100 insertions(+), 49 deletions(-)

-- 
V2 adds patch 4
2.7.4