From mboxrd@z Thu Jan  1 00:00:00 1970
From: See, Chin Liang <chin.liang.see@intel.com>
Date: Mon, 28 Nov 2016 13:37:01 +0000
Subject: [U-Boot] [PATCH v2 8/8] spi: cadence_qspi: Support specifying
 the sample edge used
In-Reply-To: <1480084688-24677-9-git-send-email-phil.edworthy@renesas.com>
References: <1480084688-24677-1-git-send-email-phil.edworthy@renesas.com>
 <1480084688-24677-9-git-send-email-phil.edworthy@renesas.com>
Message-ID: <1480340219.1847.1.camel@intel.com>
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To: u-boot@lists.denx.de

Hi Phil,

On Jum, 2016-11-25 at 14:38 +0000, Phil Edworthy wrote:
> Whilst at it, move the code to read the "sram-size" property
> into the other code that reads properties from the node, rather
> than the SF subnode.
> 
> Also change the code to use a bool for the bypass arg.
> 
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> 
> ---
> v2:
> ?Change name of DT prop and provide details of what it does.
> ?Whilst at it, move the code to read the "sram-size" property
> ?into the other code that reads properties from the node, rather
> ?than the SF subnode.
> 
> ?Also change the code to use a bool for the bypass arg.
> ---
> ?doc/device-tree-bindings/spi/spi-cadence.txt |??2 ++
> ?drivers/spi/cadence_qspi.c???????????????????| 13 +++++++++----
> ?drivers/spi/cadence_qspi.h???????????????????|??3 ++-
> ?drivers/spi/cadence_qspi_apb.c???????????????|??8 +++++++-
> ?4 files changed, 20 insertions(+), 6 deletions(-)
> 

[..]

> diff --git a/drivers/spi/cadence_qspi_apb.c
> b/drivers/spi/cadence_qspi_apb.c
> index 56ad952..e43973c 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -98,6 +98,7 @@
> ?#define????????CQSPI_REG_RD_DATA_CAPTURE_BYPASS????????BIT(0)
> ?#define????????CQSPI_REG_RD_DATA_CAPTURE_DELAY_LSB?????1
> ?#define????????CQSPI_REG_RD_DATA_CAPTURE_DELAY_MASK????0xF
> +#define????????CQSPI_REG_RD_DATA_CAPTURE_EDGE??????????BIT(5)


Actually we don't have this edge bit at SOCFPGA.
But no harm as its unused bit at SOCFPGA today

Thanks
Chin Liang