[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

Chee, Tien Fong
2016-12-07T10:36:14Z

On Sel, 2016-12-06 at 13:48 +0100, Marek Vasut wrote:
> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> > device tree build for SDMMC.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > ?arch/arm/mach-socfpga/include/mach/boot0.h |???17
> > +++++++++++++++++
> > ?configs/socfpga_arria10_defconfig??????????|???18 +++++++++++++---
> > --
> > ?2 files changed, 30 insertions(+), 5 deletions(-)
> > ?create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > new file mode 100644
> > index 0000000..8052a0b
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > @@ -0,0 +1,17 @@
> > +/*
> > + * Copyright (C) 2016, Intel Corporation
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
> > +#ifndef __BOOT0_H
> > +#define __BOOT0_H
> > +
> > +#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
> > +/* BOOT0 header information */
> > +#define ARM_SOC_BOOT0_HOOK \
> > + .fill 12, 4, 0xdeadbeef
> Seems unrelated and something that was fixed in mainline already.
>
Okay. We need the fixed sync from mainline, otherwise spl would not
working.?
> >
> > +#else
> > +#define ARM_SOC_BOOT0_HOOK
> > +#endif
> > +#endif /* __BOOT0_H */
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 422261b..755bb66 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10=y
> > ?CONFIG_DM_GPIO=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
> > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > +CONFIG_IDENT_STRING="socfpga_arria10"
> > ?# CONFIG_CMD_IMLS is not set
> > ?# CONFIG_CMD_FLASH is not set
> > ?CONFIG_CMD_GPIO=y
> > ?CONFIG_DWAPB_GPIO=y
> > -CONFIG_DM_ETH=y
> > -CONFIG_ETH_DESIGNWARE=y
> > ?CONFIG_SYS_NS16550=y
> > -CONFIG_CADENCE_QSPI=y
> > -CONFIG_DESIGNWARE_SPI=y
> > ?CONFIG_DM_MMC=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_CMD_MMC=y
> > +CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_SPL=y
> > +CONFIG_SPL_DM=y
> > +CONFIG_SPL_SIMPLE_BUS=y
> > +CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL_OF_LIBFDT=y
> > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> >
>