From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager
Date: Wed, 7 Dec 2016 11:58:48 +0000 [thread overview]
Message-ID: <1481111927.2741.32.camel@intel.com> (raw)
In-Reply-To: <a276800c-9a06-2ac1-89f8-f29103d1043d@denx.de>
On Sel, 2016-12-06 at 13:55 +0100, Marek Vasut wrote:
> On 12/06/2016 09:08 AM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Drivers for reset manager is restructured such that common
> > functions,
> > gen5 drivers and Arria10 drivers are moved to reset_manager.c,
> > reset_manager_gen5.c and reset_manager_arria10.c respectively.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > ?arch/arm/mach-socfpga/Makefile?????????????????????|???16 +-
> > ?arch/arm/mach-socfpga/include/mach/reset_manager.h |??164 ++++--
> > ?arch/arm/mach-socfpga/reset_manager.c??????????????|??114 +---
> > ?arch/arm/mach-socfpga/reset_manager_arria10.c??????|??766
> > ++++++++++++++++++++
> > ?arch/arm/mach-socfpga/reset_manager_gen5.c?????????|??116 +++
> > ?5 files changed, 1017 insertions(+), 159 deletions(-)
> > ?create mode 100644 arch/arm/mach-socfpga/reset_manager_arria10.c
> > ?create mode 100644 arch/arm/mach-socfpga/reset_manager_gen5.c
> >
> > diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> > socfpga/Makefile
> > index 809cd47..b8fcf6e 100644
> > --- a/arch/arm/mach-socfpga/Makefile
> > +++ b/arch/arm/mach-socfpga/Makefile
> > @@ -2,21 +2,27 @@
> > ?# (C) Copyright 2000-2003
> > ?# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
> > ?#
> > -# Copyright (C) 2012 Altera Corporation <www.altera.com>
> > +# Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
> > ?#
> > ?# SPDX-License-Identifier: GPL-2.0+
> > ?#
> > ?
> > ?obj-y += misc.o timer.o reset_manager.o system_manager.o
> > clock_manager.o \
> > ? ???fpga_manager.o board.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> > wrap_pll_config.o \
> > + reset_manager_gen5.o
> > ?
> > -obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += freeze_controller.o
> > wrap_iocsr_config.o \
> > + wrap_pinmux_config.o
> > wrap_sdram_config.o
> > +endif
> > ?
> > +ifdef CONFIG_TARGET_SOCFPGA_GEN5
> > ?# QTS-generated config file wrappers
> > -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> > wrap_pll_config.o
> > -obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o
> > wrap_pinmux_config.o \
> > - ???wrap_sdram_config.o
> > ?CFLAGS_wrap_iocsr_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> > ?CFLAGS_wrap_pinmux_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> > ?CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
> > ?CFLAGS_wrap_sdram_config.o +=
> > -I$(srctree)/board/$(BOARDDIR)
> > +endif
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 6225118..077391a 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -1,19 +1,32 @@
> > ?/*
> > - *??Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + *??Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
> > ? *
> > - * SPDX-License-Identifier: GPL-2.0+
> > + * SPDX-License-Identifier: GPL-2.0
> License change ?
>
i will revert it.
> >
> > ? */
> > ?
> > ?#ifndef _RESET_MANAGER_H_
> > ?#define _RESET_MANAGER_H_
> > ?
> > -void reset_cpu(ulong addr);
> > -void reset_deassert_peripherals_handoff(void);
> > +/* Common function prototypes */
> > +extern void reset_cpu(ulong addr);
> > +extern void socfpga_bridges_reset(int enable);
> > +extern void socfpga_per_reset(u32 reset, int set);
> > +extern void socfpga_per_reset_all(void);
> Drop the extern ...
>
okay.
> >
> > -void socfpga_bridges_reset(int enable);
> > -
> > -void socfpga_per_reset(u32 reset, int set);
> > -void socfpga_per_reset_all(void);
> > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > +extern void reset_deassert_peripherals_handoff(void);
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +extern void watchdog_disable(void);
> > +extern void reset_deassert_noc_ddr_scheduler(void);
> > +extern int is_wdt_in_reset(void);
> > +extern void emac_manage_reset(ulong emacbase, uint state);
> > +extern int reset_deassert_bridges_handoff(void);
> > +extern void reset_deassert_dedicated_peripherals(void);
> > +extern void reset_assert_fpga_connected_peripherals(void);
> > +extern void reset_deassert_fpga_connected_peripherals(void);
> > +extern void reset_deassert_shared_connected_peripherals(void);
> > +extern void reset_deassert_osc1wd0(void);
> > +#endif
> > ?
> > ?#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > ?struct socfpga_reset_manager {
> > @@ -29,40 +42,40 @@ struct socfpga_reset_manager {
> > ? u32 padding2[12];
> > ? u32 tstscratch;
> > ?};
> > -#else
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > ?struct socfpga_reset_manager {
> > - u32 stat;
> > - u32 ramstat;
> > - u32 miscstat;
> > - u32 ctrl;
> > - u32 hdsken;
> > - u32 hdskreq;
> > - u32 hdskack;
> > - u32 counts;
> > - u32 mpu_mod_reset;
> > - u32 per_mod_reset; /* stated as
> > per0_mod_reset in A10 datasheet */
> > - u32 per2_mod_reset; /* stated as
> > per1_mod_reset in A10 datasheet */
> > - u32 brg_mod_reset;
> > - u32 misc_mod_reset; /* stated as
> > sys_mod_reset in A10 datasheet */
> > - u32 coldmodrst;
> > - u32 nrstmodrst;
> > - u32 dbgmodrst;
> > - u32 mpuwarmmask;
> > - u32 per0warmmask;
> > - u32 per1warmmask;
> > - u32 brgwarmmask;
> > - u32 syswarmmask;
> > - u32 nrstwarmmask;
> > - u32 l3warmmask;
> > - u32 tststa;
> > - u32 tstscratch;
> > - u32 hdsktimeout;
> > - u32 hmcintr;
> > - u32 hmcintren;
> > - u32 hmcintrens;
> > - u32 hmcintrenr;
> > - u32 hmcgpout;
> > - u32 hmcgpin;
> > + volatile uint32_t??stat;
> Drop the volatile, it's useless here as it describes register layout.
> If
> it has any meaning in the code, the code is broken.
>
okay. I found that readl and writel in arm lib having volatile cast, so
volatile declaration is no longer needed.
> >
> > + volatile uint32_t??ramstat;
> > + volatile uint32_t??miscstat;
> > + volatile uint32_t??ctrl;
> > + volatile uint32_t??hdsken;
> > + volatile uint32_t??hdskreq;
> > + volatile uint32_t??hdskack;
> > + volatile uint32_t??counts;
> > + volatile uint32_t??mpumodrst;
> > + volatile uint32_t??per0modrst;
> > + volatile uint32_t??per1modrst;
> > + volatile uint32_t??brgmodrst;
> > + volatile uint32_t??sysmodrst;
> > + volatile uint32_t??coldmodrst;
> > + volatile uint32_t??nrstmodrst;
> > + volatile uint32_t??dbgmodrst;
> > + volatile uint32_t??mpuwarmmask;
> > + volatile uint32_t??per0warmmask;
> > + volatile uint32_t??per1warmmask;
> > + volatile uint32_t??brgwarmmask;
> > + volatile uint32_t??syswarmmask;
> > + volatile uint32_t??nrstwarmmask;
> > + volatile uint32_t??l3warmmask;
> > + volatile uint32_t??tststa;
> > + volatile uint32_t??tstscratch;
> > + volatile uint32_t??hdsktimeout;
> > + volatile uint32_t??hmcintr;
> > + volatile uint32_t??hmcintren;
> > + volatile uint32_t??hmcintrens;
> > + volatile uint32_t??hmcintrenr;
> > + volatile uint32_t??hmcgpout;
> > + volatile uint32_t??hmcgpin;
> > ?};
> > ?#endif
> > ?
> > @@ -113,7 +126,7 @@ struct socfpga_reset_manager {
> > ?#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 22)
> > ?#define RSTMGR_DMA RSTMGR_DEFINE(1, 28)
> > ?#define RSTMGR_SDR RSTMGR_DEFINE(1, 29)
> > -#else
> > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > ?/*
> > ? * SocFPGA Arria10 reset IDs, bank mapping is as follows:
> > ? * 0 ... mpumodrst
> > @@ -144,4 +157,71 @@ struct socfpga_reset_manager {
> > ?/* Create a human-readable reference to SoCFPGA reset. */
> > ?#define SOCFPGA_RESET(_name) RSTMGR_##_name
> > ?
> > +/* Create a human-readable reference to SoCFPGA reset. */
> > +#define SOCFPGA_RESET(_name) RSTMGR_##_name
> > +
> > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > +#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
> > +#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
> > +#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
> > +#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
> > +#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
> > +#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
> > +#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
> > +#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040
> > +#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
> > +#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK 0x00000100
> > +#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK 0x00000200
> > +#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK 0x00000400
> > +#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK 0x00000800
> > +#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK 0x00001000
> > +#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK 0x00002000
> > +#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK 0x00004000
> > +#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK 0x00008000
> > +#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
> > +#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
> > +#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
> > +#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
> > +#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
> > +#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK 0x00200000
> > +#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
> > +#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
> > +
> > +#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK 0x00000001
> > +#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK 0x00000002
> > +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK 0x00000004
> > +#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK 0x00000008
> > +#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK 0x00000010
> > +#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK 0x00000020
> > +#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
> > +#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
> > +#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
> > +#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
> > +#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
> > +#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
> > +#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
> > +#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
> > +#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
> > +#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK 0x04000000
> > +
> > +#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
> > +#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
> > +#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
> > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
> > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
> > +#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
> > +#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
> > +
> > +#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
> > +#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002
> > +#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
> > +#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
> > +#endif
> > ?#endif /* _RESET_MANAGER_H_ */
> > diff --git a/arch/arm/mach-socfpga/reset_manager.c b/arch/arm/mach-
> > socfpga/reset_manager.c
> > index d0ff6c4..0fd4221 100644
> > --- a/arch/arm/mach-socfpga/reset_manager.c
> > +++ b/arch/arm/mach-socfpga/reset_manager.c
> > @@ -1,77 +1,18 @@
> > ?/*
> > - *??Copyright (C) 2013 Altera Corporation <www.altera.com>
> > + *??Copyright (C) 2013-2016 Altera Corporation <www.altera.com>
> > ? *
> > - * SPDX-License-Identifier: GPL-2.0+
> > + * SPDX-License-Identifier: GPL-2.0
> You're changing licenses without consulting all contributors, this
> cannot be done IMO.
>
okay, i will revert it.
> >
> > ? */
> > ?
>
> [...]
>
> >
> > +void reset_deassert_dedicated_peripherals(void)
> > +{
> > + int i;
> > + u32 mask0 = 0;
> > + u32 mask1 = 0;
> > + u32 pinmux_addr = SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS;
> > + u32 mask = 0;
> > +#if defined(CONFIG_MMC)
> > + mask |= ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
> > +#elif defined(CONFIG_CADENCE_QSPI)
> > + mask |= ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK;
> > +#elif defined(CONFIG_NAND_DENALI)
> > + mask |= ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK;
> > +#else
> Shouldn't this come from OF instead of being ifdef'd ?
>
What is OF? what is your suggestion to make this function generic for
all type of flash?
> >
> > +#error "unsupported dedicated peripherals"
> > +#endif
> > + mask |= ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK;
> > +
> > + /* enable ECC OCP first */
> > + clrbits_le32(&reset_manager_base->per0modrst, mask);
> [...]
>
next prev parent reply other threads:[~2016-12-07 11:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-06 8:08 [U-Boot] [PATCH 06/10] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager Chee Tien Fong
2016-12-06 12:55 ` Marek Vasut
2016-12-07 11:58 ` Chee, Tien Fong [this message]
2016-12-07 13:58 ` Marek Vasut
2016-12-09 10:04 ` Chee, Tien Fong
2016-12-09 12:51 ` Marek Vasut
2016-12-19 6:53 ` Chee, Tien Fong
2016-12-19 7:47 ` Marek Vasut
2016-12-19 9:30 ` Chee, Tien Fong
2016-12-19 10:02 ` Marek Vasut
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