From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL
Date: Fri, 9 Dec 2016 09:46:40 +0000 [thread overview]
Message-ID: <1481276799.2741.40.camel@intel.com> (raw)
In-Reply-To: <6e86de1d-26b5-a640-5103-755fe30e8956@denx.de>
On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > >
> > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > These changes to ensure Arria10 SPL build success.
> > > Please reword the commit message, mention you're removing the
> > > Arria10
> > > bits. Still, this does not even apply on mainline, on top of what
> > > does
> > > this apply ?
> > >
> > I disabled some features temporary, so SPL build can pass and print
> > out
> > working. I will enable these features back in upcoming patches.
> > This is
> > base on 01-arria10 branch.
> But this patch seems to only enable stuff ... ?
>
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for
supporting SPI flash.
> >
> > >
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > ---
> > > > ?arch/arm/Kconfig |????8 ++++----
> > > > ?1 files changed, 4 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 220bb19..05ce8b8 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
> > > > ?config ARCH_SOCFPGA
> > > > ? bool "Altera SOCFPGA family"
> > > > ? select CPU_V7
> > > > - select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> > > > + select SUPPORT_SPL
> > > > ? select OF_CONTROL
> > > > - select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> > > > + select SPL_OF_CONTROL
> > > > ? select DM
> > > > - select DM_SPI_FLASH
> > > > - select DM_SPI
> > > > + select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> > > > + select DM_SPI if !TARGET_SOCFPGA_ARRIA10
> > > > ?
> > > > ?config TARGET_CM_T43
> > > > ? bool "Support cm_t43"
> > > >
>
next prev parent reply other threads:[~2016-12-09 9:46 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-06 7:52 [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL Chee Tien Fong
2016-12-06 7:52 ` [U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL Chee Tien Fong
2016-12-06 12:48 ` Marek Vasut
2016-12-07 10:36 ` Chee, Tien Fong
2016-12-06 7:52 ` [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2016-12-06 12:49 ` Marek Vasut
2016-12-07 10:48 ` Chee, Tien Fong
2016-12-07 13:54 ` Marek Vasut
2016-12-19 4:10 ` Chee, Tien Fong
2016-12-19 7:55 ` Marek Vasut
2016-12-19 8:40 ` Chee, Tien Fong
2016-12-19 8:43 ` Marek Vasut
2016-12-19 8:54 ` Chee, Tien Fong
2016-12-19 10:04 ` Marek Vasut
2016-12-19 10:31 ` Chee, Tien Fong
2016-12-19 12:40 ` Marek Vasut
2016-12-06 12:47 ` [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL Marek Vasut
2016-12-07 10:57 ` Chee, Tien Fong
2016-12-07 13:54 ` Marek Vasut
2016-12-09 9:46 ` Chee, Tien Fong [this message]
2016-12-09 13:02 ` Marek Vasut
2016-12-19 4:04 ` Chee, Tien Fong
2016-12-19 7:56 ` Marek Vasut
2016-12-19 8:41 ` Chee, Tien Fong
2016-12-19 8:44 ` Marek Vasut
2016-12-19 10:34 ` Chee, Tien Fong
2016-12-19 12:36 ` Marek Vasut
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