[U-Boot] [PATCH 05/10] arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Rab, 2016-12-07 at 14:57 +0100, Marek Vasut wrote:
> On 12/07/2016 12:21 PM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:51 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 09:07 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > ---
> > > > ?arch/arm/mach-socfpga/include/mach/base_addr_a10.h |???11 +-
> > > > ?arch/arm/mach-socfpga/system_manager.c?????????????|????4 +-
> > > > ?drivers/fpga/socfpga.c?????????????????????????????|????7 +-
> > > > ?include/configs/socfpga_arria10_socdk.h????????????|??152
> > > > +++++++++++++++++--
> > > > ?4 files changed, 151 insertions(+), 23 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > index 902c321..487a5dc 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
> > > > @@ -1,7 +1,7 @@
> > > > ?/*
> > > > - * Copyright (C) 2014 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
> > > > ? *
> > > > - * SPDX-License-Identifier:	GPL-2.0+
> > > > + * SPDX-License-Identifier:	GPL-2.0
> > > Can you change license this way ?
> > > 
> > Okay, i will revert this change. I discussed with Chin Liang today,
> > and
> > we decided to let owner to make the changes. How about the year
> > change
> > 2014-2016?
> To change a license of a file, you need to get an ACK from every
> single
> contributor to that file.
> 
> Year change I believe is fine.
> 
> [...]
> 
Okay, noted.
> > 
> > > 
> > > > 
> > > > @@ -89,6 +120,95 @@
> > > > ?		" root=${qspiroot} rw
> > > > rootfstype=${qspirootfstype};"\
> > > > ?		"bootm ${loadaddr} - ${fdt_addr}\0"
> > > > ?
> > > > -/* The rest of the configuration is shared */
> > > > -#include <configs/socfpga_common.h>
> > > > +/*
> > > > + * External memory configurations
> > > > + */
> > > Why is this being duplicated in board support code when it
> > > previously
> > > was in common code ? That's just wrong.
> > > 
> > I found that many conflicts between the board support code and
> > common
> > code. It is safe for Arria10 having its own setting here. What do
> > you
> > think?
> It looks like 95% of the stuff below is the same as the stuff in
> socfpga-common.h , the rest can be pulled from DT or ifdef'd .
> 
If socfpga-common.h is preferred, then i have to use ifdef method, are
you ok with this? However, this would look a bit messy, because some
#define setting in here, and other #define setting in socfpga-common.h
under same category or peripheral configuration group.
> > 
> > > 
> > > > 
> > > > +#define PHYS_SDRAM_1???????????????????0x0
> > > > +#define PHYS_SDRAM_1_SIZE??????????????0x80000000
> > > > +#define CONFIG_SYS_SDRAM_BASE??????????0
> > > > +#define CONFIG_NR_DRAM_BANKS???????????1
> > > > +#define CONFIG_SYS_MEMTEST_START???????0
> > > > +#define CONFIG_SYS_MEMTEST_END?????????0x100000
> > > > +
> > > > +/*
> > > > + * Serial / UART configurations
> > > > + */
> > > > +#define CONFIG_SYS_NS16550_SERIAL
> > > > +#define CONFIG_SYS_NS16550_MEM32
> > > > +#define CONFIG_SYS_NS16550_REG_SIZE????-4
> > > > +#define CONFIG_SYS_NS16550_COM1????????SOCFPGA_UART1_ADDRESS
> > > > +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,
> > > > 57600, 115200}
> > > > +#define CONFIG_SYS_NS16550_CLK?????????(50000000)
> > > > +#define CONFIG_CONS_INDEX??????????????1
> > > > +#define CONFIG_BAUDRATE????????????????115200
> > > > +
> > > > +/*
> > > > + * L4 OSC1 Timer 0
> > > > + */
> > > > +/* This timer use eosc1 where the clock frequency is fixed
> > > > + * throughout any condition */
> > > > +#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_
> > > > ADDR
> > > > ESS
> > > > +/* address of timer counter value */
> > > > +#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE
> > > > +
> > > > 0x4)
> > > > +/* reload value when timer count to zero */
> > > > +#define TIMER_LOAD_VAL			0xFFFFFFFF
> > > > +/* Clocks source frequency to timer */
> > > > +#define CONFIG_SYS_TIMER_RATE		(25000000)
> > > > +
> > > > +/* DesignWare timer is a countdown timer */
> > > > +#define CONFIG_SYS_TIMER_COUNTS_DOWN
> > > > +
> > > > +/*
> > > > + * L4 Watchdog configurations
> > > > + */
> > > > +#ifdef CONFIG_HW_WATCHDOG
> > > > +#define CONFIG_DESIGNWARE_WATCHDOG
> > > > +#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRES
> > > > S
> > > > +#define CONFIG_HPS_CLK_OSC1_HZ	25000000
> > > > +#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK
> > > > _OSC
> > > > 1_HZ / 1000)
> > > > +#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
> > > > +#endif
> > > > +
> > > > +/*
> > > > + * SDMMC configurations
> > > > + */
> > > > +#ifdef CONFIG_CMD_MMC
> > > > +#define CONFIG_MMC
> > > > +#define CONFIG_BOUNCE_BUFFER
> > > > +#define CONFIG_GENERIC_MMC
> > > > +#define CONFIG_DWMMC
> > > > +#define CONFIG_SOCFPGA_DWMMC
> > > > +#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH????????1024
> > > > +#define CONFIG_SYS_MMC_MAX_BLK_COUNT???????????256
> > > > +#endif
> > > > +
> > > > +/*
> > > > + * Flash configurations
> > > > + */
> > > > +#define CONFIG_SYS_MAX_FLASH_BANKS?????1
> > > > +#define CONFIG_SYS_NO_FLASH
> > > > +
> > > > +/* SPL configuration */
> > > > +#define CONFIG_SPL_FRAMEWORK
> > > > +#define CONFIG_SPL_RAM_DEVICE
> > > > +#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RA
> > > > M_AD
> > > > DR
> > > > +#define CONFIG_SPL_MAX_SIZE			CONFIG_SYS_
> > > > INIT
> > > > _RAM_SIZE
> > > > +
> > > > +#ifdef CONFIG_SPL_BUILD
> > > > +#define CONFIG_SYS_MALLOC_SIMPLE
> > > > +#endif
> > > > +
> > > > +#ifdef CONFIG_SPL_NAND_DENALI
> > > > +#define CONFIG_SPL_NAND_SUPPORT
> > > > +#endif
> > > > +
> > > > +/*
> > > > + * Stack setup
> > > > + */
> > > > +#define CONFIG_SPL_STACK			CONFIG_SYS_INI
> > > > T_SP
> > > > _ADDR
> > > > +
> > > > +/* SPL SDMMC boot support */
> > > > +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION?????1
> > > > +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME????????????????"u-
> > > > boot-
> > > > dtb.img"
> > > > +
> > > > ?#endif	/* __CONFIG_H */
> > > > 
>