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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro
Date: Mon, 19 Dec 2016 10:31:17 +0000	[thread overview]
Message-ID: <1482143476.2382.35.camel@intel.com> (raw)
In-Reply-To: <9cd8c0ca-7377-9319-e015-d49345f6a248@denx.de>

On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote:
> On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
> > > 
> > > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > > > > 
> > > > > > > > > > These compat macros would be used by clock manager
> > > > > > > > > > and
> > > > > > > > > > pin
> > > > > > > > > > mux
> > > > > > > > > > drivers
> > > > > > > > > > to look the required HW info from DTS for hardware
> > > > > > > > > > initialization.
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel
> > > > > > > > > > .com
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > > > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > > > > > > > ---
> > > > > > > > > > ?include/fdtdec.h |????8 ++++++++
> > > > > > > > > > ?lib/fdtdec.c?????|????2 ++
> > > > > > > > > > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > > > > > > > index 27887c8..68cb199 100644
> > > > > > > > > > --- a/include/fdtdec.h
> > > > > > > > > > +++ b/include/fdtdec.h
> > > > > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > > > > > > > > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/*
> > > > > > > > > > Intel
> > > > > > > > > > FSP
> > > > > > > > > > memory-
> > > > > > > > > > down params */
> > > > > > > > > > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/*
> > > > > > > > > > Intel
> > > > > > > > > > Ivy
> > > > > > > > > > Bridge
> > > > > > > > > > FSP
> > > > > > > > > > */
> > > > > > > > > > ?	COMPAT_SUNXI_NAND,		/* SUNXI
> > > > > > > > > > NAND
> > > > > > > > > > controller
> > > > > > > > > > */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_CLK,	/*
> > > > > > > > > > SoCFPGA
> > > > > > > > > > Clock
> > > > > > > > > > initialization */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > pinctrl-
> > > > > > > > > > single */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
> > > > > > > > > > /*
> > > > > > > > > > Arria10
> > > > > > > > > > hps2fpga bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
> > > > > > > > > > Arria10
> > > > > > > > > > lwhps2fpga bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
> > > > > > > > > > /*
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2hps bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM0 bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM1 bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM2 bridge */
> > > > > > > > > Is all of this needed ? You're only adding two
> > > > > > > > > entries in
> > > > > > > > > the
> > > > > > > > > FDTDEC
> > > > > > > > > below.
> > > > > > > > > 
> > > > > > > > This is to avoid compilation error, we have some
> > > > > > > > functions
> > > > > > > > ported
> > > > > > > > from
> > > > > > > > our internal branch, which using above COMPAT macro.
> > > > > > > > Soon,
> > > > > > > > in
> > > > > > > > upcoming
> > > > > > > > patches, we will need those functions and more entries
> > > > > > > > will
> > > > > > > > be
> > > > > > > > added
> > > > > > > > into FDTDEC below.
> > > > > > > You can add the compat strings when you really need them.
> > > > > > > Still,
> > > > > > > with
> > > > > > > DM, you shouldn't even need them AFAIK.
> > > > > > > 
> > > > > > We have some drivers in these series of patches contain
> > > > > > some
> > > > > > COMPAT
> > > > > > strings, without these compact strings, the compilation
> > > > > > would
> > > > > > fail
> > > > > > due
> > > > > > to error compact string is not defined.
> > > > > All of them ? Mind you, with DM you should not need to add
> > > > > those
> > > > > at
> > > > > all.
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > I think having compact string
> > > > > > would giving us flexbility to put our nodes where we want
> > > > > > without
> > > > > > worrying to break our existing codes?
> > > > > Which existing codes ?
> > > > > 
> > > > let say we have version A, we found the node based on COMPAT
> > > > STRING.
> > > > One day, we move the node to somewhere else in version B, we
> > > > still
> > > > can
> > > > find them based on COMPAT STRING without checking the node
> > > > path.
> > > > What
> > > > do you think?
> > > I do not understand what you're trying to tell me here. The DM
> > > core
> > > will
> > > walk the DT and bind drivers according to compat strings, so if
> > > you ever move a node, it will still be bound.
> > > 
> > > Also, you didn't answer my question -- which existing codes do
> > > you
> > > refer
> > > to. Or is this some hypothetical concern ?
> > > 
> > existing codes is hypothetical example, when someone move the node
> > somewhere, the DM still can find the node based on COMPAT STRING.
> Correct. If you only have hypothetical concerns, we'll deal with
> those
> when they become real.
> 
> > 
> > Without COMPAT STRING, we need to change the driver code for the
> > node
> > path right?
> Uh no, the driver must never encode a fixed DT path. It should match
> on
> the compat string and that's it. And the compat string is part of the
> driver, not the FDT decoder. AFAIK, the strings in FDT decoder are
> just
> temporary helpers during the DT conversion of drivers.
> 
Yeah, i have bridges reset driver in this series patches, and these
drivers contains those COMPAT string. Without those COMPAT string,
compilation would fail. It could be i missed to add those FDT entries,
i can add those FDT entries in next version.

  reply	other threads:[~2016-12-19 10:31 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-06  7:52 [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL Chee Tien Fong
2016-12-06  7:52 ` [U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL Chee Tien Fong
2016-12-06 12:48   ` Marek Vasut
2016-12-07 10:36     ` Chee, Tien Fong
2016-12-06  7:52 ` [U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2016-12-06 12:49   ` Marek Vasut
2016-12-07 10:48     ` Chee, Tien Fong
2016-12-07 13:54       ` Marek Vasut
2016-12-19  4:10         ` Chee, Tien Fong
2016-12-19  7:55           ` Marek Vasut
2016-12-19  8:40             ` Chee, Tien Fong
2016-12-19  8:43               ` Marek Vasut
2016-12-19  8:54                 ` Chee, Tien Fong
2016-12-19 10:04                   ` Marek Vasut
2016-12-19 10:31                     ` Chee, Tien Fong [this message]
2016-12-19 12:40                       ` Marek Vasut
2016-12-06 12:47 ` [U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL Marek Vasut
2016-12-07 10:57   ` Chee, Tien Fong
2016-12-07 13:54     ` Marek Vasut
2016-12-09  9:46       ` Chee, Tien Fong
2016-12-09 13:02         ` Marek Vasut
2016-12-19  4:04           ` Chee, Tien Fong
2016-12-19  7:56             ` Marek Vasut
2016-12-19  8:41               ` Chee, Tien Fong
2016-12-19  8:44                 ` Marek Vasut
2016-12-19 10:34                   ` Chee, Tien Fong
2016-12-19 12:36                     ` Marek Vasut

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