[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee Tien Fong]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These changes to ensure Arria10 SPL build success.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
 arch/arm/Kconfig |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 220bb19..05ce8b8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
 	select OF_CONTROL
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
 	select DM
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
 
 config TARGET_CM_T43
 	bool "Support cm_t43"
-- 
1.7.7.4

[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee Tien Fong]

From: Tien Fong Chee <tien.fong.chee@intel.com>

Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
 arch/arm/mach-socfpga/include/mach/boot0.h |   17 +++++++++++++++++
 configs/socfpga_arria10_defconfig          |   18 +++++++++++++-----
 2 files changed, 30 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h

diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
new file mode 100644
index 0000000..8052a0b
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/boot0.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.fill 12, 4, 0xdeadbeef
+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+#endif /* __BOOT0_H */
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
index 422261b..755bb66 100644
--- a/configs/socfpga_arria10_defconfig
+++ b/configs/socfpga_arria10_defconfig
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
-- 
1.7.7.4

[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Marek Vasut]

On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> Enhanced defconfig file for Arria10 to enable SPL build and supporting
> device tree build for SDMMC.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Tien Fong <skywindctf@gmail.com>
> ---
>  arch/arm/mach-socfpga/include/mach/boot0.h |   17 +++++++++++++++++
>  configs/socfpga_arria10_defconfig          |   18 +++++++++++++-----
>  2 files changed, 30 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h b/arch/arm/mach-socfpga/include/mach/boot0.h
> new file mode 100644
> index 0000000..8052a0b
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> @@ -0,0 +1,17 @@
> +/*
> + * Copyright (C) 2016, Intel Corporation
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __BOOT0_H
> +#define __BOOT0_H
> +
> +#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
> +/* BOOT0 header information */
> +#define ARM_SOC_BOOT0_HOOK	\
> +	.fill 12, 4, 0xdeadbeef

Seems unrelated and something that was fixed in mainline already.

> +#else
> +#define ARM_SOC_BOOT0_HOOK
> +#endif
> +#endif /* __BOOT0_H */
> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
> index 422261b..755bb66 100644
> --- a/configs/socfpga_arria10_defconfig
> +++ b/configs/socfpga_arria10_defconfig
> @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
>  CONFIG_TARGET_SOCFPGA_ARRIA10=y
>  CONFIG_DM_GPIO=y
>  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
> +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> +CONFIG_IDENT_STRING="socfpga_arria10"
>  # CONFIG_CMD_IMLS is not set
>  # CONFIG_CMD_FLASH is not set
>  CONFIG_CMD_GPIO=y
>  CONFIG_DWAPB_GPIO=y
> -CONFIG_DM_ETH=y
> -CONFIG_ETH_DESIGNWARE=y
>  CONFIG_SYS_NS16550=y
> -CONFIG_CADENCE_QSPI=y
> -CONFIG_DESIGNWARE_SPI=y
>  CONFIG_DM_MMC=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_CMD_MMC=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SPL=y
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_SIMPLE_BUS=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL_SERIAL_SUPPORT=y
> +CONFIG_SPL_OF_LIBFDT=y
> +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 03/10] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

[Chee, Tien Fong]

On Sel, 2016-12-06 at 13:48 +0100, Marek Vasut wrote:
> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Enhanced defconfig file for Arria10 to enable SPL build and
> > supporting
> > device tree build for SDMMC.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > ?arch/arm/mach-socfpga/include/mach/boot0.h |???17
> > +++++++++++++++++
> > ?configs/socfpga_arria10_defconfig??????????|???18 +++++++++++++---
> > --
> > ?2 files changed, 30 insertions(+), 5 deletions(-)
> > ?create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > new file mode 100644
> > index 0000000..8052a0b
> > --- /dev/null
> > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > @@ -0,0 +1,17 @@
> > +/*
> > + * Copyright (C) 2016, Intel Corporation
> > + *
> > + * SPDX-License-Identifier:	GPL-2.0
> > + */
> > +
> > +#ifndef __BOOT0_H
> > +#define __BOOT0_H
> > +
> > +#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
> > +/* BOOT0 header information */
> > +#define ARM_SOC_BOOT0_HOOK	\
> > +	.fill 12, 4, 0xdeadbeef
> Seems unrelated and something that was fixed in mainline already.
> 
Okay. We need the fixed sync from mainline, otherwise spl would not
working.?
> > 
> > +#else
> > +#define ARM_SOC_BOOT0_HOOK
> > +#endif
> > +#endif /* __BOOT0_H */
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 422261b..755bb66 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10=y
> > ?CONFIG_DM_GPIO=y
> > ?CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> > -CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
> > +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > +CONFIG_IDENT_STRING="socfpga_arria10"
> > ?# CONFIG_CMD_IMLS is not set
> > ?# CONFIG_CMD_FLASH is not set
> > ?CONFIG_CMD_GPIO=y
> > ?CONFIG_DWAPB_GPIO=y
> > -CONFIG_DM_ETH=y
> > -CONFIG_ETH_DESIGNWARE=y
> > ?CONFIG_SYS_NS16550=y
> > -CONFIG_CADENCE_QSPI=y
> > -CONFIG_DESIGNWARE_SPI=y
> > ?CONFIG_DM_MMC=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_CMD_MMC=y
> > +CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_SPL=y
> > +CONFIG_SPL_DM=y
> > +CONFIG_SPL_SIMPLE_BUS=y
> > +CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL_SERIAL_SUPPORT=y
> > +CONFIG_SPL_OF_LIBFDT=y
> > +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y
> > 
> 

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee Tien Fong]

From: Tien Fong Chee <tien.fong.chee@intel.com>

These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/include/fdtdec.h b/include/fdtdec.h
index 27887c8..68cb199 100644
--- a/include/fdtdec.h
+++ b/include/fdtdec.h
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10 hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10 lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10 fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10 fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10 fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10 fpga2SDRAM2 bridge */
 
 	COMPAT_COUNT,
 };
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4defb90..09a1db4 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)
-- 
1.7.7.4

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> These compat macros would be used by clock manager and pin mux drivers
> to look the required HW info from DTS for hardware initialization.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Tien Fong <skywindctf@gmail.com>
> ---
>  include/fdtdec.h |    8 ++++++++
>  lib/fdtdec.c     |    2 ++
>  2 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/include/fdtdec.h b/include/fdtdec.h
> index 27887c8..68cb199 100644
> --- a/include/fdtdec.h
> +++ b/include/fdtdec.h
> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
>  	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
> +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-single */
> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10 hps2fpga bridge */
> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10 lwhps2fpga bridge */
> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10 fpga2hps bridge */
> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10 fpga2SDRAM0 bridge */
> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10 fpga2SDRAM1 bridge */
> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10 fpga2SDRAM2 bridge */

Is all of this needed ? You're only adding two entries in the FDTDEC below.

>  
>  	COMPAT_COUNT,
>  };
> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> index 4defb90..09a1db4 100644
> --- a/lib/fdtdec.c
> +++ b/lib/fdtdec.c
> @@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
>  	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>  	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>  	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
> +	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
> +	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
>  };
>  
>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee, Tien Fong]

On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > These compat macros would be used by clock manager and pin mux
> > drivers
> > to look the required HW info from DTS for hardware initialization.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > ?include/fdtdec.h |????8 ++++++++
> > ?lib/fdtdec.c?????|????2 ++
> > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > 
> > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > index 27887c8..68cb199 100644
> > --- a/include/fdtdec.h
> > +++ b/include/fdtdec.h
> > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-
> > down params */
> > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP
> > */
> > ?	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller
> > */
> > +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
> > initialization */
> > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-
> > single */
> > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10
> > hps2fpga bridge */
> > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
> > lwhps2fpga bridge */
> > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10
> > fpga2hps bridge */
> > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10
> > fpga2SDRAM0 bridge */
> > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10
> > fpga2SDRAM1 bridge */
> > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10
> > fpga2SDRAM2 bridge */
> Is all of this needed ? You're only adding two entries in the FDTDEC
> below.
> 
This is to avoid compilation error, we have some functions ported from
our internal branch, which using above COMPAT macro. Soon, in upcoming
patches, we will need those functions and more entries will be added
into FDTDEC below.
> > 
> > ?
> > ?	COMPAT_COUNT,
> > ?};
> > diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> > index 4defb90..09a1db4 100644
> > --- a/lib/fdtdec.c
> > +++ b/lib/fdtdec.c
> > @@ -66,6 +66,8 @@ static const char * const
> > compat_names[COMPAT_COUNT] = {
> > ?	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
> > ?	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
> > ?	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
> > +	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
> > +	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
> > ?};
> > ?
> > ?const char *fdtdec_get_compatible(enum fdt_compat_id id)
> > 
> 

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> These compat macros would be used by clock manager and pin mux
>>> drivers
>>> to look the required HW info from DTS for hardware initialization.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>> Cc: Tien Fong <skywindctf@gmail.com>
>>> ---
>>>  include/fdtdec.h |    8 ++++++++
>>>  lib/fdtdec.c     |    2 ++
>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>
>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>> index 27887c8..68cb199 100644
>>> --- a/include/fdtdec.h
>>> +++ b/include/fdtdec.h
>>> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>>>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-
>>> down params */
>>>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP
>>> */
>>>  	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller
>>> */
>>> +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
>>> initialization */
>>> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-
>>> single */
>>> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10
>>> hps2fpga bridge */
>>> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
>>> lwhps2fpga bridge */
>>> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10
>>> fpga2hps bridge */
>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10
>>> fpga2SDRAM0 bridge */
>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10
>>> fpga2SDRAM1 bridge */
>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10
>>> fpga2SDRAM2 bridge */
>> Is all of this needed ? You're only adding two entries in the FDTDEC
>> below.
>>
> This is to avoid compilation error, we have some functions ported from
> our internal branch, which using above COMPAT macro. Soon, in upcoming
> patches, we will need those functions and more entries will be added
> into FDTDEC below.

You can add the compat strings when you really need them. Still, with
DM, you shouldn't even need them AFAIK.

>>>
>>>  
>>>  	COMPAT_COUNT,
>>>  };
>>> diff --git a/lib/fdtdec.c b/lib/fdtdec.c
>>> index 4defb90..09a1db4 100644
>>> --- a/lib/fdtdec.c
>>> +++ b/lib/fdtdec.c
>>> @@ -66,6 +66,8 @@ static const char * const
>>> compat_names[COMPAT_COUNT] = {
>>>  	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
>>>  	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
>>>  	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
>>> +	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
>>> +	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
>>>  };
>>>  
>>>  const char *fdtdec_get_compatible(enum fdt_compat_id id)
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee, Tien Fong]

On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > These compat macros would be used by clock manager and pin mux
> > > > drivers
> > > > to look the required HW info from DTS for hardware
> > > > initialization.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > ---
> > > > ?include/fdtdec.h |????8 ++++++++
> > > > ?lib/fdtdec.c?????|????2 ++
> > > > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > index 27887c8..68cb199 100644
> > > > --- a/include/fdtdec.h
> > > > +++ b/include/fdtdec.h
> > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
> > > > memory-
> > > > down params */
> > > > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge
> > > > FSP
> > > > */
> > > > ?	COMPAT_SUNXI_NAND,		/* SUNXI NAND
> > > > controller
> > > > */
> > > > +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
> > > > initialization */
> > > > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
> > > > pinctrl-
> > > > single */
> > > > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
> > > > Arria10
> > > > hps2fpga bridge */
> > > > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
> > > > lwhps2fpga bridge */
> > > > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
> > > > Arria10
> > > > fpga2hps bridge */
> > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
> > > > Arria10
> > > > fpga2SDRAM0 bridge */
> > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
> > > > Arria10
> > > > fpga2SDRAM1 bridge */
> > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
> > > > Arria10
> > > > fpga2SDRAM2 bridge */
> > > Is all of this needed ? You're only adding two entries in the
> > > FDTDEC
> > > below.
> > > 
> > This is to avoid compilation error, we have some functions ported
> > from
> > our internal branch, which using above COMPAT macro. Soon, in
> > upcoming
> > patches, we will need those functions and more entries will be
> > added
> > into FDTDEC below.
> You can add the compat strings when you really need them. Still, with
> DM, you shouldn't even need them AFAIK.
> 
We have some drivers in these series of patches contain some COMPAT
strings, without these compact strings, the compilation would fail due
to error compact string is not defined. I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
> > 
> > > 
> > > > 
> > > > 
> > > > ?
> > > > ?	COMPAT_COUNT,
> > > > ?};
> > > > diff --git a/lib/fdtdec.c b/lib/fdtdec.c
> > > > index 4defb90..09a1db4 100644
> > > > --- a/lib/fdtdec.c
> > > > +++ b/lib/fdtdec.c
> > > > @@ -66,6 +66,8 @@ static const char * const
> > > > compat_names[COMPAT_COUNT] = {
> > > > ?	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-
> > > > mdp"),
> > > > ?	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
> > > > ?	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
> > > > +	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
> > > > +	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-
> > > > single"),
> > > > ?};
> > > > ?
> > > > ?const char *fdtdec_get_compatible(enum fdt_compat_id id)
> > > > 
> 

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> These compat macros would be used by clock manager and pin mux
>>>>> drivers
>>>>> to look the required HW info from DTS for hardware
>>>>> initialization.
>>>>>
>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>> Cc: Tien Fong <skywindctf@gmail.com>
>>>>> ---
>>>>>  include/fdtdec.h |    8 ++++++++
>>>>>  lib/fdtdec.c     |    2 ++
>>>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>>>
>>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>>> index 27887c8..68cb199 100644
>>>>> --- a/include/fdtdec.h
>>>>> +++ b/include/fdtdec.h
>>>>> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>>>>>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
>>>>> memory-
>>>>> down params */
>>>>>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge
>>>>> FSP
>>>>> */
>>>>>  	COMPAT_SUNXI_NAND,		/* SUNXI NAND
>>>>> controller
>>>>> */
>>>>> +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
>>>>> initialization */
>>>>> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
>>>>> pinctrl-
>>>>> single */
>>>>> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
>>>>> Arria10
>>>>> hps2fpga bridge */
>>>>> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
>>>>> lwhps2fpga bridge */
>>>>> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
>>>>> Arria10
>>>>> fpga2hps bridge */
>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
>>>>> Arria10
>>>>> fpga2SDRAM0 bridge */
>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
>>>>> Arria10
>>>>> fpga2SDRAM1 bridge */
>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
>>>>> Arria10
>>>>> fpga2SDRAM2 bridge */
>>>> Is all of this needed ? You're only adding two entries in the
>>>> FDTDEC
>>>> below.
>>>>
>>> This is to avoid compilation error, we have some functions ported
>>> from
>>> our internal branch, which using above COMPAT macro. Soon, in
>>> upcoming
>>> patches, we will need those functions and more entries will be
>>> added
>>> into FDTDEC below.
>> You can add the compat strings when you really need them. Still, with
>> DM, you shouldn't even need them AFAIK.
>>
> We have some drivers in these series of patches contain some COMPAT
> strings, without these compact strings, the compilation would fail due
> to error compact string is not defined.

All of them ? Mind you, with DM you should not need to add those at all.

> I think having compact string
> would giving us flexbility to put our nodes where we want without
> worrying to break our existing codes?

Which existing codes ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee, Tien Fong]

On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
> On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > These compat macros would be used by clock manager and pin
> > > > > > mux
> > > > > > drivers
> > > > > > to look the required HW info from DTS for hardware
> > > > > > initialization.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > > > ---
> > > > > > ?include/fdtdec.h |????8 ++++++++
> > > > > > ?lib/fdtdec.c?????|????2 ++
> > > > > > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > > > > > 
> > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > > > index 27887c8..68cb199 100644
> > > > > > --- a/include/fdtdec.h
> > > > > > +++ b/include/fdtdec.h
> > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > > > > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
> > > > > > memory-
> > > > > > down params */
> > > > > > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy
> > > > > > Bridge
> > > > > > FSP
> > > > > > */
> > > > > > ?	COMPAT_SUNXI_NAND,		/* SUNXI NAND
> > > > > > controller
> > > > > > */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
> > > > > > initialization */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
> > > > > > pinctrl-
> > > > > > single */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
> > > > > > Arria10
> > > > > > hps2fpga bridge */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
> > > > > > lwhps2fpga bridge */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
> > > > > > Arria10
> > > > > > fpga2hps bridge */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
> > > > > > Arria10
> > > > > > fpga2SDRAM0 bridge */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
> > > > > > Arria10
> > > > > > fpga2SDRAM1 bridge */
> > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
> > > > > > Arria10
> > > > > > fpga2SDRAM2 bridge */
> > > > > Is all of this needed ? You're only adding two entries in the
> > > > > FDTDEC
> > > > > below.
> > > > > 
> > > > This is to avoid compilation error, we have some functions
> > > > ported
> > > > from
> > > > our internal branch, which using above COMPAT macro. Soon, in
> > > > upcoming
> > > > patches, we will need those functions and more entries will be
> > > > added
> > > > into FDTDEC below.
> > > You can add the compat strings when you really need them. Still,
> > > with
> > > DM, you shouldn't even need them AFAIK.
> > > 
> > We have some drivers in these series of patches contain some COMPAT
> > strings, without these compact strings, the compilation would fail
> > due
> > to error compact string is not defined.
> All of them ? Mind you, with DM you should not need to add those at
> all.
> 
> > 
> > I think having compact string
> > would giving us flexbility to put our nodes where we want without
> > worrying to break our existing codes?
> Which existing codes ?
> 
let say we have version A, we found the node based on COMPAT STRING.
One day, we move the node to somewhere else in version B, we still can
find them based on COMPAT STRING without checking the node path. What
do you think?

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
>> On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>
>>>>>>> These compat macros would be used by clock manager and pin
>>>>>>> mux
>>>>>>> drivers
>>>>>>> to look the required HW info from DTS for hardware
>>>>>>> initialization.
>>>>>>>
>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>>> Cc: Tien Fong <skywindctf@gmail.com>
>>>>>>> ---
>>>>>>>  include/fdtdec.h |    8 ++++++++
>>>>>>>  lib/fdtdec.c     |    2 ++
>>>>>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>>>>>
>>>>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>>>>> index 27887c8..68cb199 100644
>>>>>>> --- a/include/fdtdec.h
>>>>>>> +++ b/include/fdtdec.h
>>>>>>> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>>>>>>>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
>>>>>>> memory-
>>>>>>> down params */
>>>>>>>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy
>>>>>>> Bridge
>>>>>>> FSP
>>>>>>> */
>>>>>>>  	COMPAT_SUNXI_NAND,		/* SUNXI NAND
>>>>>>> controller
>>>>>>> */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
>>>>>>> initialization */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
>>>>>>> pinctrl-
>>>>>>> single */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
>>>>>>> Arria10
>>>>>>> hps2fpga bridge */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
>>>>>>> lwhps2fpga bridge */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
>>>>>>> Arria10
>>>>>>> fpga2hps bridge */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
>>>>>>> Arria10
>>>>>>> fpga2SDRAM0 bridge */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
>>>>>>> Arria10
>>>>>>> fpga2SDRAM1 bridge */
>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
>>>>>>> Arria10
>>>>>>> fpga2SDRAM2 bridge */
>>>>>> Is all of this needed ? You're only adding two entries in the
>>>>>> FDTDEC
>>>>>> below.
>>>>>>
>>>>> This is to avoid compilation error, we have some functions
>>>>> ported
>>>>> from
>>>>> our internal branch, which using above COMPAT macro. Soon, in
>>>>> upcoming
>>>>> patches, we will need those functions and more entries will be
>>>>> added
>>>>> into FDTDEC below.
>>>> You can add the compat strings when you really need them. Still,
>>>> with
>>>> DM, you shouldn't even need them AFAIK.
>>>>
>>> We have some drivers in these series of patches contain some COMPAT
>>> strings, without these compact strings, the compilation would fail
>>> due
>>> to error compact string is not defined.
>> All of them ? Mind you, with DM you should not need to add those at
>> all.
>>
>>>
>>> I think having compact string
>>> would giving us flexbility to put our nodes where we want without
>>> worrying to break our existing codes?
>> Which existing codes ?
>>
> let say we have version A, we found the node based on COMPAT STRING.
> One day, we move the node to somewhere else in version B, we still can
> find them based on COMPAT STRING without checking the node path. What
> do you think?

I do not understand what you're trying to tell me here. The DM core will
walk the DT and bind drivers according to compat strings, so if
you ever move a node, it will still be bound.

Also, you didn't answer my question -- which existing codes do you refer
to. Or is this some hypothetical concern ?

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee, Tien Fong]

On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
> On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
> > > 
> > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > > 
> > > > > > > > These compat macros would be used by clock manager and
> > > > > > > > pin
> > > > > > > > mux
> > > > > > > > drivers
> > > > > > > > to look the required HW info from DTS for hardware
> > > > > > > > initialization.
> > > > > > > > 
> > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com
> > > > > > > > >
> > > > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > > > > > ---
> > > > > > > > ?include/fdtdec.h |????8 ++++++++
> > > > > > > > ?lib/fdtdec.c?????|????2 ++
> > > > > > > > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > > > > > index 27887c8..68cb199 100644
> > > > > > > > --- a/include/fdtdec.h
> > > > > > > > +++ b/include/fdtdec.h
> > > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > > > > > > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel
> > > > > > > > FSP
> > > > > > > > memory-
> > > > > > > > down params */
> > > > > > > > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel
> > > > > > > > Ivy
> > > > > > > > Bridge
> > > > > > > > FSP
> > > > > > > > */
> > > > > > > > ?	COMPAT_SUNXI_NAND,		/* SUNXI
> > > > > > > > NAND
> > > > > > > > controller
> > > > > > > > */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA
> > > > > > > > Clock
> > > > > > > > initialization */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/
> > > > > > > > *
> > > > > > > > pinctrl-
> > > > > > > > single */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
> > > > > > > > /*
> > > > > > > > Arria10
> > > > > > > > hps2fpga bridge */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
> > > > > > > > Arria10
> > > > > > > > lwhps2fpga bridge */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
> > > > > > > > /*
> > > > > > > > Arria10
> > > > > > > > fpga2hps bridge */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/
> > > > > > > > *
> > > > > > > > Arria10
> > > > > > > > fpga2SDRAM0 bridge */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/
> > > > > > > > *
> > > > > > > > Arria10
> > > > > > > > fpga2SDRAM1 bridge */
> > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/
> > > > > > > > *
> > > > > > > > Arria10
> > > > > > > > fpga2SDRAM2 bridge */
> > > > > > > Is all of this needed ? You're only adding two entries in
> > > > > > > the
> > > > > > > FDTDEC
> > > > > > > below.
> > > > > > > 
> > > > > > This is to avoid compilation error, we have some functions
> > > > > > ported
> > > > > > from
> > > > > > our internal branch, which using above COMPAT macro. Soon,
> > > > > > in
> > > > > > upcoming
> > > > > > patches, we will need those functions and more entries will
> > > > > > be
> > > > > > added
> > > > > > into FDTDEC below.
> > > > > You can add the compat strings when you really need them.
> > > > > Still,
> > > > > with
> > > > > DM, you shouldn't even need them AFAIK.
> > > > > 
> > > > We have some drivers in these series of patches contain some
> > > > COMPAT
> > > > strings, without these compact strings, the compilation would
> > > > fail
> > > > due
> > > > to error compact string is not defined.
> > > All of them ? Mind you, with DM you should not need to add those
> > > at
> > > all.
> > > 
> > > > 
> > > > 
> > > > I think having compact string
> > > > would giving us flexbility to put our nodes where we want
> > > > without
> > > > worrying to break our existing codes?
> > > Which existing codes ?
> > > 
> > let say we have version A, we found the node based on COMPAT
> > STRING.
> > One day, we move the node to somewhere else in version B, we still
> > can
> > find them based on COMPAT STRING without checking the node path.
> > What
> > do you think?
> I do not understand what you're trying to tell me here. The DM core
> will
> walk the DT and bind drivers according to compat strings, so if
> you ever move a node, it will still be bound.
> 
> Also, you didn't answer my question -- which existing codes do you
> refer
> to. Or is this some hypothetical concern ?
> 
existing codes is hypothetical example, when someone move the node
somewhere, the DM still can find the node based on COMPAT STRING.
Without COMPAT STRING, we need to change the driver code for the node
path right?

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>>>
>>>>>>>>> These compat macros would be used by clock manager and
>>>>>>>>> pin
>>>>>>>>> mux
>>>>>>>>> drivers
>>>>>>>>> to look the required HW info from DTS for hardware
>>>>>>>>> initialization.
>>>>>>>>>
>>>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com
>>>>>>>>>>
>>>>>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>>> Cc: Tien Fong <skywindctf@gmail.com>
>>>>>>>>> ---
>>>>>>>>>  include/fdtdec.h |    8 ++++++++
>>>>>>>>>  lib/fdtdec.c     |    2 ++
>>>>>>>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>>>>>>> index 27887c8..68cb199 100644
>>>>>>>>> --- a/include/fdtdec.h
>>>>>>>>> +++ b/include/fdtdec.h
>>>>>>>>> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>>>>>>>>>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel
>>>>>>>>> FSP
>>>>>>>>> memory-
>>>>>>>>> down params */
>>>>>>>>>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel
>>>>>>>>> Ivy
>>>>>>>>> Bridge
>>>>>>>>> FSP
>>>>>>>>> */
>>>>>>>>>  	COMPAT_SUNXI_NAND,		/* SUNXI
>>>>>>>>> NAND
>>>>>>>>> controller
>>>>>>>>> */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA
>>>>>>>>> Clock
>>>>>>>>> initialization */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/
>>>>>>>>> *
>>>>>>>>> pinctrl-
>>>>>>>>> single */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
>>>>>>>>> /*
>>>>>>>>> Arria10
>>>>>>>>> hps2fpga bridge */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
>>>>>>>>> Arria10
>>>>>>>>> lwhps2fpga bridge */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
>>>>>>>>> /*
>>>>>>>>> Arria10
>>>>>>>>> fpga2hps bridge */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/
>>>>>>>>> *
>>>>>>>>> Arria10
>>>>>>>>> fpga2SDRAM0 bridge */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/
>>>>>>>>> *
>>>>>>>>> Arria10
>>>>>>>>> fpga2SDRAM1 bridge */
>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/
>>>>>>>>> *
>>>>>>>>> Arria10
>>>>>>>>> fpga2SDRAM2 bridge */
>>>>>>>> Is all of this needed ? You're only adding two entries in
>>>>>>>> the
>>>>>>>> FDTDEC
>>>>>>>> below.
>>>>>>>>
>>>>>>> This is to avoid compilation error, we have some functions
>>>>>>> ported
>>>>>>> from
>>>>>>> our internal branch, which using above COMPAT macro. Soon,
>>>>>>> in
>>>>>>> upcoming
>>>>>>> patches, we will need those functions and more entries will
>>>>>>> be
>>>>>>> added
>>>>>>> into FDTDEC below.
>>>>>> You can add the compat strings when you really need them.
>>>>>> Still,
>>>>>> with
>>>>>> DM, you shouldn't even need them AFAIK.
>>>>>>
>>>>> We have some drivers in these series of patches contain some
>>>>> COMPAT
>>>>> strings, without these compact strings, the compilation would
>>>>> fail
>>>>> due
>>>>> to error compact string is not defined.
>>>> All of them ? Mind you, with DM you should not need to add those
>>>> at
>>>> all.
>>>>
>>>>>
>>>>>
>>>>> I think having compact string
>>>>> would giving us flexbility to put our nodes where we want
>>>>> without
>>>>> worrying to break our existing codes?
>>>> Which existing codes ?
>>>>
>>> let say we have version A, we found the node based on COMPAT
>>> STRING.
>>> One day, we move the node to somewhere else in version B, we still
>>> can
>>> find them based on COMPAT STRING without checking the node path.
>>> What
>>> do you think?
>> I do not understand what you're trying to tell me here. The DM core
>> will
>> walk the DT and bind drivers according to compat strings, so if
>> you ever move a node, it will still be bound.
>>
>> Also, you didn't answer my question -- which existing codes do you
>> refer
>> to. Or is this some hypothetical concern ?
>>
> existing codes is hypothetical example, when someone move the node
> somewhere, the DM still can find the node based on COMPAT STRING.

Correct. If you only have hypothetical concerns, we'll deal with those
when they become real.

> Without COMPAT STRING, we need to change the driver code for the node
> path right?

Uh no, the driver must never encode a fixed DT path. It should match on
the compat string and that's it. And the compat string is part of the
driver, not the FDT decoder. AFAIK, the strings in FDT decoder are just
temporary helpers during the DT conversion of drivers.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Chee, Tien Fong]

On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote:
> On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
> > > 
> > > On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > > > > 
> > > > > > > > > > These compat macros would be used by clock manager
> > > > > > > > > > and
> > > > > > > > > > pin
> > > > > > > > > > mux
> > > > > > > > > > drivers
> > > > > > > > > > to look the required HW info from DTS for hardware
> > > > > > > > > > initialization.
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel
> > > > > > > > > > .com
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > Cc: Marek Vasut <marex@denx.de>
> > > > > > > > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > > > > > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > > > > > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > > > > > > > ---
> > > > > > > > > > ?include/fdtdec.h |????8 ++++++++
> > > > > > > > > > ?lib/fdtdec.c?????|????2 ++
> > > > > > > > > > ?2 files changed, 10 insertions(+), 0 deletions(-)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/include/fdtdec.h b/include/fdtdec.h
> > > > > > > > > > index 27887c8..68cb199 100644
> > > > > > > > > > --- a/include/fdtdec.h
> > > > > > > > > > +++ b/include/fdtdec.h
> > > > > > > > > > @@ -155,6 +155,14 @@ enum fdt_compat_id {
> > > > > > > > > > ?	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/*
> > > > > > > > > > Intel
> > > > > > > > > > FSP
> > > > > > > > > > memory-
> > > > > > > > > > down params */
> > > > > > > > > > ?	COMPAT_INTEL_IVYBRIDGE_FSP,	/*
> > > > > > > > > > Intel
> > > > > > > > > > Ivy
> > > > > > > > > > Bridge
> > > > > > > > > > FSP
> > > > > > > > > > */
> > > > > > > > > > ?	COMPAT_SUNXI_NAND,		/* SUNXI
> > > > > > > > > > NAND
> > > > > > > > > > controller
> > > > > > > > > > */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_CLK,	/*
> > > > > > > > > > SoCFPGA
> > > > > > > > > > Clock
> > > > > > > > > > initialization */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > pinctrl-
> > > > > > > > > > single */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
> > > > > > > > > > /*
> > > > > > > > > > Arria10
> > > > > > > > > > hps2fpga bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
> > > > > > > > > > Arria10
> > > > > > > > > > lwhps2fpga bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
> > > > > > > > > > /*
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2hps bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM0 bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM1 bridge */
> > > > > > > > > > +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		
> > > > > > > > > > /
> > > > > > > > > > *
> > > > > > > > > > Arria10
> > > > > > > > > > fpga2SDRAM2 bridge */
> > > > > > > > > Is all of this needed ? You're only adding two
> > > > > > > > > entries in
> > > > > > > > > the
> > > > > > > > > FDTDEC
> > > > > > > > > below.
> > > > > > > > > 
> > > > > > > > This is to avoid compilation error, we have some
> > > > > > > > functions
> > > > > > > > ported
> > > > > > > > from
> > > > > > > > our internal branch, which using above COMPAT macro.
> > > > > > > > Soon,
> > > > > > > > in
> > > > > > > > upcoming
> > > > > > > > patches, we will need those functions and more entries
> > > > > > > > will
> > > > > > > > be
> > > > > > > > added
> > > > > > > > into FDTDEC below.
> > > > > > > You can add the compat strings when you really need them.
> > > > > > > Still,
> > > > > > > with
> > > > > > > DM, you shouldn't even need them AFAIK.
> > > > > > > 
> > > > > > We have some drivers in these series of patches contain
> > > > > > some
> > > > > > COMPAT
> > > > > > strings, without these compact strings, the compilation
> > > > > > would
> > > > > > fail
> > > > > > due
> > > > > > to error compact string is not defined.
> > > > > All of them ? Mind you, with DM you should not need to add
> > > > > those
> > > > > at
> > > > > all.
> > > > > 
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > I think having compact string
> > > > > > would giving us flexbility to put our nodes where we want
> > > > > > without
> > > > > > worrying to break our existing codes?
> > > > > Which existing codes ?
> > > > > 
> > > > let say we have version A, we found the node based on COMPAT
> > > > STRING.
> > > > One day, we move the node to somewhere else in version B, we
> > > > still
> > > > can
> > > > find them based on COMPAT STRING without checking the node
> > > > path.
> > > > What
> > > > do you think?
> > > I do not understand what you're trying to tell me here. The DM
> > > core
> > > will
> > > walk the DT and bind drivers according to compat strings, so if
> > > you ever move a node, it will still be bound.
> > > 
> > > Also, you didn't answer my question -- which existing codes do
> > > you
> > > refer
> > > to. Or is this some hypothetical concern ?
> > > 
> > existing codes is hypothetical example, when someone move the node
> > somewhere, the DM still can find the node based on COMPAT STRING.
> Correct. If you only have hypothetical concerns, we'll deal with
> those
> when they become real.
> 
> > 
> > Without COMPAT STRING, we need to change the driver code for the
> > node
> > path right?
> Uh no, the driver must never encode a fixed DT path. It should match
> on
> the compat string and that's it. And the compat string is part of the
> driver, not the FDT decoder. AFAIK, the strings in FDT decoder are
> just
> temporary helpers during the DT conversion of drivers.
> 
Yeah, i have bridges reset driver in this series patches, and these
drivers contains those COMPAT string. Without those COMPAT string,
compilation would fail. It could be i missed to add those FDT entries,
i can add those FDT entries in next version.

[U-Boot] [PATCH 04/10] arm: socfpga: arria10: Added clock manager and pin mux compat macro

[Marek Vasut]

On 12/19/2016 11:31 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 11:04 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:54 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 09:43 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/19/2016 09:40 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Isn, 2016-12-19 at 08:55 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/19/2016 05:10 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 12/07/2016 11:48 AM, Chee, Tien Fong wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On Sel, 2016-12-06 at 13:49 +0100, Marek Vasut wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>>>>>
>>>>>>>>>>> These compat macros would be used by clock manager
>>>>>>>>>>> and
>>>>>>>>>>> pin
>>>>>>>>>>> mux
>>>>>>>>>>> drivers
>>>>>>>>>>> to look the required HW info from DTS for hardware
>>>>>>>>>>> initialization.
>>>>>>>>>>>
>>>>>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel
>>>>>>>>>>> .com
>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>> Cc: Marek Vasut <marex@denx.de>
>>>>>>>>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>>>>>>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>>>>>>>>> Cc: Tien Fong <skywindctf@gmail.com>
>>>>>>>>>>> ---
>>>>>>>>>>>  include/fdtdec.h |    8 ++++++++
>>>>>>>>>>>  lib/fdtdec.c     |    2 ++
>>>>>>>>>>>  2 files changed, 10 insertions(+), 0 deletions(-)
>>>>>>>>>>>
>>>>>>>>>>> diff --git a/include/fdtdec.h b/include/fdtdec.h
>>>>>>>>>>> index 27887c8..68cb199 100644
>>>>>>>>>>> --- a/include/fdtdec.h
>>>>>>>>>>> +++ b/include/fdtdec.h
>>>>>>>>>>> @@ -155,6 +155,14 @@ enum fdt_compat_id {
>>>>>>>>>>>  	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/*
>>>>>>>>>>> Intel
>>>>>>>>>>> FSP
>>>>>>>>>>> memory-
>>>>>>>>>>> down params */
>>>>>>>>>>>  	COMPAT_INTEL_IVYBRIDGE_FSP,	/*
>>>>>>>>>>> Intel
>>>>>>>>>>> Ivy
>>>>>>>>>>> Bridge
>>>>>>>>>>> FSP
>>>>>>>>>>> */
>>>>>>>>>>>  	COMPAT_SUNXI_NAND,		/* SUNXI
>>>>>>>>>>> NAND
>>>>>>>>>>> controller
>>>>>>>>>>> */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_CLK,	/*
>>>>>>>>>>> SoCFPGA
>>>>>>>>>>> Clock
>>>>>>>>>>> initialization */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	
>>>>>>>>>>> /
>>>>>>>>>>> *
>>>>>>>>>>> pinctrl-
>>>>>>>>>>> single */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
>>>>>>>>>>> /*
>>>>>>>>>>> Arria10
>>>>>>>>>>> hps2fpga bridge */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
>>>>>>>>>>> Arria10
>>>>>>>>>>> lwhps2fpga bridge */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
>>>>>>>>>>> /*
>>>>>>>>>>> Arria10
>>>>>>>>>>> fpga2hps bridge */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR0,		
>>>>>>>>>>> /
>>>>>>>>>>> *
>>>>>>>>>>> Arria10
>>>>>>>>>>> fpga2SDRAM0 bridge */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR1,		
>>>>>>>>>>> /
>>>>>>>>>>> *
>>>>>>>>>>> Arria10
>>>>>>>>>>> fpga2SDRAM1 bridge */
>>>>>>>>>>> +	COMPAT_ALTERA_SOCFPGA_F2SDR2,		
>>>>>>>>>>> /
>>>>>>>>>>> *
>>>>>>>>>>> Arria10
>>>>>>>>>>> fpga2SDRAM2 bridge */
>>>>>>>>>> Is all of this needed ? You're only adding two
>>>>>>>>>> entries in
>>>>>>>>>> the
>>>>>>>>>> FDTDEC
>>>>>>>>>> below.
>>>>>>>>>>
>>>>>>>>> This is to avoid compilation error, we have some
>>>>>>>>> functions
>>>>>>>>> ported
>>>>>>>>> from
>>>>>>>>> our internal branch, which using above COMPAT macro.
>>>>>>>>> Soon,
>>>>>>>>> in
>>>>>>>>> upcoming
>>>>>>>>> patches, we will need those functions and more entries
>>>>>>>>> will
>>>>>>>>> be
>>>>>>>>> added
>>>>>>>>> into FDTDEC below.
>>>>>>>> You can add the compat strings when you really need them.
>>>>>>>> Still,
>>>>>>>> with
>>>>>>>> DM, you shouldn't even need them AFAIK.
>>>>>>>>
>>>>>>> We have some drivers in these series of patches contain
>>>>>>> some
>>>>>>> COMPAT
>>>>>>> strings, without these compact strings, the compilation
>>>>>>> would
>>>>>>> fail
>>>>>>> due
>>>>>>> to error compact string is not defined.
>>>>>> All of them ? Mind you, with DM you should not need to add
>>>>>> those
>>>>>> at
>>>>>> all.
>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> I think having compact string
>>>>>>> would giving us flexbility to put our nodes where we want
>>>>>>> without
>>>>>>> worrying to break our existing codes?
>>>>>> Which existing codes ?
>>>>>>
>>>>> let say we have version A, we found the node based on COMPAT
>>>>> STRING.
>>>>> One day, we move the node to somewhere else in version B, we
>>>>> still
>>>>> can
>>>>> find them based on COMPAT STRING without checking the node
>>>>> path.
>>>>> What
>>>>> do you think?
>>>> I do not understand what you're trying to tell me here. The DM
>>>> core
>>>> will
>>>> walk the DT and bind drivers according to compat strings, so if
>>>> you ever move a node, it will still be bound.
>>>>
>>>> Also, you didn't answer my question -- which existing codes do
>>>> you
>>>> refer
>>>> to. Or is this some hypothetical concern ?
>>>>
>>> existing codes is hypothetical example, when someone move the node
>>> somewhere, the DM still can find the node based on COMPAT STRING.
>> Correct. If you only have hypothetical concerns, we'll deal with
>> those
>> when they become real.
>>
>>>
>>> Without COMPAT STRING, we need to change the driver code for the
>>> node
>>> path right?
>> Uh no, the driver must never encode a fixed DT path. It should match
>> on
>> the compat string and that's it. And the compat string is part of the
>> driver, not the FDT decoder. AFAIK, the strings in FDT decoder are
>> just
>> temporary helpers during the DT conversion of drivers.
>>
> Yeah, i have bridges reset driver in this series patches, and these
> drivers contains those COMPAT string. Without those COMPAT string,
> compilation would fail. It could be i missed to add those FDT entries,
> i can add those FDT entries in next version.

OK, then add those compat strings with the matching driver if and only
if it is needed.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> These changes to ensure Arria10 SPL build success.

Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what does
this apply ?

> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Tien Fong <skywindctf@gmail.com>
> ---
>  arch/arm/Kconfig |    8 ++++----
>  1 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 220bb19..05ce8b8 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
>  config ARCH_SOCFPGA
>  	bool "Altera SOCFPGA family"
>  	select CPU_V7
> -	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> +	select SUPPORT_SPL
>  	select OF_CONTROL
> -	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> +	select SPL_OF_CONTROL
>  	select DM
> -	select DM_SPI_FLASH
> -	select DM_SPI
> +	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> +	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
>  
>  config TARGET_CM_T43
>  	bool "Support cm_t43"
> 


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee, Tien Fong]

On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > These changes to ensure Arria10 SPL build success.
> Please reword the commit message, mention you're removing the Arria10
> bits. Still, this does not even apply on mainline, on top of what
> does
> this apply ?
> 
I disabled some features temporary, so SPL build can pass and print out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Chin Liang See <chin.liang.see@intel.com>
> > Cc: Tien Fong <skywindctf@gmail.com>
> > ---
> > ?arch/arm/Kconfig |????8 ++++----
> > ?1 files changed, 4 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 220bb19..05ce8b8 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
> > ?config ARCH_SOCFPGA
> > ?	bool "Altera SOCFPGA family"
> > ?	select CPU_V7
> > -	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> > +	select SUPPORT_SPL
> > ?	select OF_CONTROL
> > -	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> > +	select SPL_OF_CONTROL
> > ?	select DM
> > -	select DM_SPI_FLASH
> > -	select DM_SPI
> > +	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> > +	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
> > ?
> > ?config TARGET_CM_T43
> > ?	bool "Support cm_t43"
> > 
> 

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> These changes to ensure Arria10 SPL build success.
>> Please reword the commit message, mention you're removing the Arria10
>> bits. Still, this does not even apply on mainline, on top of what
>> does
>> this apply ?
>>
> I disabled some features temporary, so SPL build can pass and print out
> working. I will enable these features back in upcoming patches. This is
> base on 01-arria10 branch.

But this patch seems to only enable stuff ... ?

>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>> Cc: Tien Fong <skywindctf@gmail.com>
>>> ---
>>>  arch/arm/Kconfig |    8 ++++----
>>>  1 files changed, 4 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>>> index 220bb19..05ce8b8 100644
>>> --- a/arch/arm/Kconfig
>>> +++ b/arch/arm/Kconfig
>>> @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
>>>  config ARCH_SOCFPGA
>>>  	bool "Altera SOCFPGA family"
>>>  	select CPU_V7
>>> -	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
>>> +	select SUPPORT_SPL
>>>  	select OF_CONTROL
>>> -	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
>>> +	select SPL_OF_CONTROL
>>>  	select DM
>>> -	select DM_SPI_FLASH
>>> -	select DM_SPI
>>> +	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
>>> +	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
>>>  
>>>  config TARGET_CM_T43
>>>  	bool "Support cm_t43"
>>>


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee, Tien Fong]

On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > 
> > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > These changes to ensure Arria10 SPL build success.
> > > Please reword the commit message, mention you're removing the
> > > Arria10
> > > bits. Still, this does not even apply on mainline, on top of what
> > > does
> > > this apply ?
> > > 
> > I disabled some features temporary, so SPL build can pass and print
> > out
> > working. I will enable these features back in upcoming patches.
> > This is
> > base on 01-arria10 branch.
> But this patch seems to only enable stuff ... ?
> 
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for
supporting SPI flash.
> > 
> > > 
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > > Cc: Tien Fong <skywindctf@gmail.com>
> > > > ---
> > > > ?arch/arm/Kconfig |????8 ++++----
> > > > ?1 files changed, 4 insertions(+), 4 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > > index 220bb19..05ce8b8 100644
> > > > --- a/arch/arm/Kconfig
> > > > +++ b/arch/arm/Kconfig
> > > > @@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
> > > > ?config ARCH_SOCFPGA
> > > > ?	bool "Altera SOCFPGA family"
> > > > ?	select CPU_V7
> > > > -	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
> > > > +	select SUPPORT_SPL
> > > > ?	select OF_CONTROL
> > > > -	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
> > > > +	select SPL_OF_CONTROL
> > > > ?	select DM
> > > > -	select DM_SPI_FLASH
> > > > -	select DM_SPI
> > > > +	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
> > > > +	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
> > > > ?
> > > > ?config TARGET_CM_T43
> > > > ?	bool "Support cm_t43"
> > > > 
> 

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>
>>>>>
>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>
>>>>> These changes to ensure Arria10 SPL build success.
>>>> Please reword the commit message, mention you're removing the
>>>> Arria10
>>>> bits. Still, this does not even apply on mainline, on top of what
>>>> does
>>>> this apply ?
>>>>
>>> I disabled some features temporary, so SPL build can pass and print
>>> out
>>> working. I will enable these features back in upcoming patches.
>>> This is
>>> base on 01-arria10 branch.
>> But this patch seems to only enable stuff ... ?
>>
> Enable the spl. Disable SPI flash temporary, for preventing build
> failed, but this will be enabled back with upcoming patches for
> supporting SPI flash.

What's the problem with SPI flash ? I thought it's the same block as in
C/A 5 ?


-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee, Tien Fong]

On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > 
> > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > 
> > > > > > These changes to ensure Arria10 SPL build success.
> > > > > Please reword the commit message, mention you're removing the
> > > > > Arria10
> > > > > bits. Still, this does not even apply on mainline, on top of
> > > > > what
> > > > > does
> > > > > this apply ?
> > > > > 
> > > > I disabled some features temporary, so SPL build can pass and
> > > > print
> > > > out
> > > > working. I will enable these features back in upcoming patches.
> > > > This is
> > > > base on 01-arria10 branch.
> > > But this patch seems to only enable stuff ... ?
> > > 
> > Enable the spl. Disable SPI flash temporary, for preventing build
> > failed, but this will be enabled back with upcoming patches for
> > supporting SPI flash.
> What's the problem with SPI flash ? I thought it's the same block as
> in
> C/A 5 ?
> 
Some compilation error, but i haven't checked it out what errors
causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once
booting from SDMMC working, i will work to boot from QSPI and NAND
too.
> 

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
>> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>
>>>>>>> These changes to ensure Arria10 SPL build success.
>>>>>> Please reword the commit message, mention you're removing the
>>>>>> Arria10
>>>>>> bits. Still, this does not even apply on mainline, on top of
>>>>>> what
>>>>>> does
>>>>>> this apply ?
>>>>>>
>>>>> I disabled some features temporary, so SPL build can pass and
>>>>> print
>>>>> out
>>>>> working. I will enable these features back in upcoming patches.
>>>>> This is
>>>>> base on 01-arria10 branch.
>>>> But this patch seems to only enable stuff ... ?
>>>>
>>> Enable the spl. Disable SPI flash temporary, for preventing build
>>> failed, but this will be enabled back with upcoming patches for
>>> supporting SPI flash.
>> What's the problem with SPI flash ? I thought it's the same block as
>> in
>> C/A 5 ?
>>
> Some compilation error, but i haven't checked it out what errors
> causing the build failed. My plan is to have SPL and print out working,
> then following boot from SDMMC, FPGA configuration, DDR up. Once
> booting from SDMMC working, i will work to boot from QSPI and NAND
> too.

MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee, Tien Fong]

On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
> On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> > 
> > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> > > 
> > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > > 
> > > > > > > > These changes to ensure Arria10 SPL build success.
> > > > > > > Please reword the commit message, mention you're removing
> > > > > > > the
> > > > > > > Arria10
> > > > > > > bits. Still, this does not even apply on mainline, on top
> > > > > > > of
> > > > > > > what
> > > > > > > does
> > > > > > > this apply ?
> > > > > > > 
> > > > > > I disabled some features temporary, so SPL build can pass
> > > > > > and
> > > > > > print
> > > > > > out
> > > > > > working. I will enable these features back in upcoming
> > > > > > patches.
> > > > > > This is
> > > > > > base on 01-arria10 branch.
> > > > > But this patch seems to only enable stuff ... ?
> > > > > 
> > > > Enable the spl. Disable SPI flash temporary, for preventing
> > > > build
> > > > failed, but this will be enabled back with upcoming patches for
> > > > supporting SPI flash.
> > > What's the problem with SPI flash ? I thought it's the same block
> > > as
> > > in
> > > C/A 5 ?
> > > 
> > Some compilation error, but i haven't checked it out what errors
> > causing the build failed. My plan is to have SPL and print out
> > working,
> > then following boot from SDMMC, FPGA configuration, DDR up. Once
> > booting from SDMMC working, i will work to boot from QSPI and NAND
> > too.
> MW is now closed, so you can focus on fixing the CQSPI too, it
> shouldn't
> be too hard.
> 
What is MW?

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
>> On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
>>>
>>> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>>>
>>>>>>>>> These changes to ensure Arria10 SPL build success.
>>>>>>>> Please reword the commit message, mention you're removing
>>>>>>>> the
>>>>>>>> Arria10
>>>>>>>> bits. Still, this does not even apply on mainline, on top
>>>>>>>> of
>>>>>>>> what
>>>>>>>> does
>>>>>>>> this apply ?
>>>>>>>>
>>>>>>> I disabled some features temporary, so SPL build can pass
>>>>>>> and
>>>>>>> print
>>>>>>> out
>>>>>>> working. I will enable these features back in upcoming
>>>>>>> patches.
>>>>>>> This is
>>>>>>> base on 01-arria10 branch.
>>>>>> But this patch seems to only enable stuff ... ?
>>>>>>
>>>>> Enable the spl. Disable SPI flash temporary, for preventing
>>>>> build
>>>>> failed, but this will be enabled back with upcoming patches for
>>>>> supporting SPI flash.
>>>> What's the problem with SPI flash ? I thought it's the same block
>>>> as
>>>> in
>>>> C/A 5 ?
>>>>
>>> Some compilation error, but i haven't checked it out what errors
>>> causing the build failed. My plan is to have SPL and print out
>>> working,
>>> then following boot from SDMMC, FPGA configuration, DDR up. Once
>>> booting from SDMMC working, i will work to boot from QSPI and NAND
>>> too.
>> MW is now closed, so you can focus on fixing the CQSPI too, it
>> shouldn't
>> be too hard.
>>
> What is MW?
> 
Merge Window

-- 
Best regards,
Marek Vasut

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Chee, Tien Fong]

On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
> > > 
> > > On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > > > > 
> > > > > > > > > > These changes to ensure Arria10 SPL build success.
> > > > > > > > > Please reword the commit message, mention you're
> > > > > > > > > removing
> > > > > > > > > the
> > > > > > > > > Arria10
> > > > > > > > > bits. Still, this does not even apply on mainline, on
> > > > > > > > > top
> > > > > > > > > of
> > > > > > > > > what
> > > > > > > > > does
> > > > > > > > > this apply ?
> > > > > > > > > 
> > > > > > > > I disabled some features temporary, so SPL build can
> > > > > > > > pass
> > > > > > > > and
> > > > > > > > print
> > > > > > > > out
> > > > > > > > working. I will enable these features back in upcoming
> > > > > > > > patches.
> > > > > > > > This is
> > > > > > > > base on 01-arria10 branch.
> > > > > > > But this patch seems to only enable stuff ... ?
> > > > > > > 
> > > > > > Enable the spl. Disable SPI flash temporary, for preventing
> > > > > > build
> > > > > > failed, but this will be enabled back with upcoming patches
> > > > > > for
> > > > > > supporting SPI flash.
> > > > > What's the problem with SPI flash ? I thought it's the same
> > > > > block
> > > > > as
> > > > > in
> > > > > C/A 5 ?
> > > > > 
> > > > Some compilation error, but i haven't checked it out what
> > > > errors
> > > > causing the build failed. My plan is to have SPL and print out
> > > > working,
> > > > then following boot from SDMMC, FPGA configuration, DDR up.
> > > > Once
> > > > booting from SDMMC working, i will work to boot from QSPI and
> > > > NAND
> > > > too.
> > > MW is now closed, so you can focus on fixing the CQSPI too, it
> > > shouldn't
> > > be too hard.
> > > 
> > What is MW?
> > 
> Merge Window

just for comfirmation, are you means rebase to master of u-boot-
socfpga.git or denx master? I think former,right?

[U-Boot] [PATCH 02/10] arm: socfpga: arria10: Added config option build for SPL

[Marek Vasut]

On 12/19/2016 11:34 AM, Chee, Tien Fong wrote:
> On Isn, 2016-12-19 at 09:44 +0100, Marek Vasut wrote:
>> On 12/19/2016 09:41 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2016-12-19 at 08:56 +0100, Marek Vasut wrote:
>>>>
>>>> On 12/19/2016 05:04 AM, Chee, Tien Fong wrote:
>>>>>
>>>>>
>>>>> On Jum, 2016-12-09 at 14:02 +0100, Marek Vasut wrote:
>>>>>>
>>>>>>
>>>>>> On 12/09/2016 10:46 AM, Chee, Tien Fong wrote:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> On Rab, 2016-12-07 at 14:54 +0100, Marek Vasut wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>> On 12/07/2016 11:57 AM, Chee, Tien Fong wrote:
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> On Sel, 2016-12-06 at 13:47 +0100, Marek Vasut wrote:
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> On 12/06/2016 08:52 AM, Chee Tien Fong wrote:
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>>>>>>>>>
>>>>>>>>>>> These changes to ensure Arria10 SPL build success.
>>>>>>>>>> Please reword the commit message, mention you're
>>>>>>>>>> removing
>>>>>>>>>> the
>>>>>>>>>> Arria10
>>>>>>>>>> bits. Still, this does not even apply on mainline, on
>>>>>>>>>> top
>>>>>>>>>> of
>>>>>>>>>> what
>>>>>>>>>> does
>>>>>>>>>> this apply ?
>>>>>>>>>>
>>>>>>>>> I disabled some features temporary, so SPL build can
>>>>>>>>> pass
>>>>>>>>> and
>>>>>>>>> print
>>>>>>>>> out
>>>>>>>>> working. I will enable these features back in upcoming
>>>>>>>>> patches.
>>>>>>>>> This is
>>>>>>>>> base on 01-arria10 branch.
>>>>>>>> But this patch seems to only enable stuff ... ?
>>>>>>>>
>>>>>>> Enable the spl. Disable SPI flash temporary, for preventing
>>>>>>> build
>>>>>>> failed, but this will be enabled back with upcoming patches
>>>>>>> for
>>>>>>> supporting SPI flash.
>>>>>> What's the problem with SPI flash ? I thought it's the same
>>>>>> block
>>>>>> as
>>>>>> in
>>>>>> C/A 5 ?
>>>>>>
>>>>> Some compilation error, but i haven't checked it out what
>>>>> errors
>>>>> causing the build failed. My plan is to have SPL and print out
>>>>> working,
>>>>> then following boot from SDMMC, FPGA configuration, DDR up.
>>>>> Once
>>>>> booting from SDMMC working, i will work to boot from QSPI and
>>>>> NAND
>>>>> too.
>>>> MW is now closed, so you can focus on fixing the CQSPI too, it
>>>> shouldn't
>>>> be too hard.
>>>>
>>> What is MW?
>>>
>> Merge Window
> 
> just for comfirmation, are you means rebase to master of u-boot-
> socfpga.git or denx master? I think former,right?
> 
You can use either now, u-boot-socfpga has no patches queued and
u-boot.git is more up-to-date .

-- 
Best regards,
Marek Vasut