[U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10

Chee Tien Fong
2016-12-28T06:34:34Z

From: Tien Fong Chee <tien.fong.chee@intel.com>

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
changes for v2
- Separate patch for adding some HW base address for Arria 10.
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -36,10 +36,13 @@
#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000

#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
--
2.2.2