From: Chee Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 23/30] arm: socfpga: arria10: Added some hardware base address for Arria 10
Date: Wed, 28 Dec 2016 14:34:34 +0800 [thread overview]
Message-ID: <1482906881-8120-23-git-send-email-tien.fong.chee@intel.com> (raw)
In-Reply-To: <1482906881-8120-1-git-send-email-tien.fong.chee@intel.com>
From: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Tien Fong <skywindctf@gmail.com>
---
changes for v2
- Separate patch for adding some HW base address for Arria 10.
---
arch/arm/mach-socfpga/include/mach/base_addr_a10.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
index 902c321..2d66580 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_a10.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -36,10 +36,13 @@
#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
#define SOCFPGA_UART0_ADDRESS 0xffc02000
#define SOCFPGA_OSC1TIMER0_ADDRESS 0xffd00000
+#define SOCFPGA_OSC1TIMER1_ADDRESS 0xffd00100
#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
#define SOCFPGA_SDR_ADDRESS 0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST 0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST 0xffd13500
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300
--
2.2.2
next prev parent reply other threads:[~2016-12-28 6:34 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-28 6:34 [U-Boot] [PATCH v2 01/30] arm: socfpga: arria10: add additional i2c nodes for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 02/30] arm: socfpga: arria10: add sdram defines " Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 03/30] arm: socfpga: arria10: add board files for the Arria10 SoCDK Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 04/30] arm: socfpga: arria10: add system manager defines Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 05/30] arm: socfpga: arria10: add misc functions for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 06/30] arm: socfpga: arria10: add socfpga_arria10_socdk config Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 07/30] arm: socfpga: arria10: add socfpga_arria10_defconfig Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 08/30] arm: socfpga: arria10: add config option build for arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 09/30] arm: socfpga: add define for bootinfo bsel bit shift Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 10/30] arm: socfpga: arria10: add reset manager for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 11/30] arm: socfpga: wrap system manager functions for A5/C5 devices Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 12/30] arm: socfpga: arria10: don't build GEN5 sdram for arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 13/30] arm: socfpga: arria10 fpga does not have bridges mapped Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 14/30] arm: socfpga: arria10: remove board_init and s_init Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 15/30] arm: socfpga: combine clrbits/setbits into a single clrsetbits Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 16/30] arm: socfpga: add reset manager defines for Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 17/30] arm: socfpga: arria10: update dwmac reset function to support Arria10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 18/30] arm: socfpga: stratix10: Add SOCFPGA Stratix10 base address Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 19/30] ARM:dts: Added device tree for socfpga arria10 development kit sdmmc Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 20/30] arm: socfpga: arria10: Enable SPL for Arria 10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 21/30] arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL Chee Tien Fong
2016-12-28 23:51 ` Marek Vasut
2016-12-29 4:54 ` Chee, Tien Fong
2016-12-30 19:04 ` Marek Vasut
2017-01-03 5:38 ` Chee, Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 22/30] arm: socfpga: arria10: Added clock manager and pin mux compat macro Chee Tien Fong
2016-12-28 6:34 ` Chee Tien Fong [this message]
2016-12-28 6:34 ` [U-Boot] [PATCH v2 24/30] arm: socfpga: arria10: Added support for Arria 10 socdk Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 25/30] arm: socfpga: arria10: Added drivers for Arria10 Reset Manager Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 26/30] arm: socfpga: arria10: Added miscellaneous drivers for Arria 10 Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 27/30] arm: socfpga: arria10: Added drivers for Arria10 clock manager Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 28/30] arm: socfpga: arria10: Added drivers for Arria10 pinmux/pins configuration Chee Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl Chee Tien Fong
2016-12-30 12:14 ` Dinh Nguyen
2017-01-03 5:43 ` Chee, Tien Fong
2016-12-28 6:34 ` [U-Boot] [PATCH v2 30/30] arm: socfpga: arria10: Enable fpga driver build for SPL Chee Tien Fong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1482906881-8120-23-git-send-email-tien.fong.chee@intel.com \
--to=tien.fong.chee@intel.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox