From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Tue, 3 Jan 2017 05:43:52 +0000 Subject: [U-Boot] [PATCH v2 29/30] arm: socfpga: arria10: Added Arria10 critical HW initialization to spl In-Reply-To: <254867a0-3df5-6e1a-fb4a-9a89396b32b4@kernel.org> References: <1482906881-8120-1-git-send-email-tien.fong.chee@intel.com> <1482906881-8120-29-git-send-email-tien.fong.chee@intel.com> <254867a0-3df5-6e1a-fb4a-9a89396b32b4@kernel.org> Message-ID: <1483422232.2665.8.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Jum, 2016-12-30 at 06:14 -0600, Dinh Nguyen wrote: > > On 12/28/2016 12:34 AM, Chee Tien Fong wrote: > > > > From: Tien Fong Chee > > > > This patch adding the Arria10 critical hardware initialization > > before > > enabling console print out in spl. > > > > Signed-off-by: Tien Fong Chee > > Cc: Marek Vasut > > Cc: Dinh Nguyen > > Cc: Chin Liang See > > Cc: Tien Fong > > --- > > Changes for V2 > > - Release UART from reset before enalbing console, and reverting > > license > > ? changes. > > --- > > ?arch/arm/mach-socfpga/spl.c | 84 > > +++++++++++++++++++++++++++++++++++++++++++-- > > ?1 file changed, 82 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach- > > socfpga/spl.c > > index fec4c7a..9e27f82 100644 > > --- a/arch/arm/mach-socfpga/spl.c > > +++ b/arch/arm/mach-socfpga/spl.c > > @@ -1,5 +1,5 @@ > > ?/* > > - *??Copyright (C) 2012 Altera Corporation > > + *??Copyright (C) 2012-2016 Altera Corporation > > ? * > > ? * SPDX-License-Identifier: GPL-2.0+ > > ? */ > > @@ -19,22 +19,32 @@ > > ?#include > > ?#include > > ?#include > > +#include > > +#include > > +#include > > +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > +#include > > +#endif > > ? > > ?DECLARE_GLOBAL_DATA_PTR; > > ? > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > ?static struct pl310_regs *const pl310 = > > ? (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > ?static struct scu_registers *scu_regs = > > ? (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; > > ?static struct nic301_registers *nic301_regs = > > ? (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; > > -static struct socfpga_system_manager *sysmgr_regs = > > +#endif > > + > > +static const struct socfpga_system_manager *sysmgr_regs = > > ? (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > > ? > > ?u32 spl_boot_device(void) > > ?{ > > ? const u32 bsel = readl(&sysmgr_regs->bootinfo); > > ? > > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) > > ? switch (bsel & 0x7) { > > ? case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > ? return BOOT_DEVICE_RAM; > > @@ -55,6 +65,24 @@ u32 spl_boot_device(void) > > ? printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > ? hang(); > > ? } > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) > > + switch ((bsel>>12) & 0x7) { > Spaces around the '>>'. > > > > > + case 0x1: /* FPGA (HPS2FPGA Bridge) */ > > + return BOOT_DEVICE_RAM; > > + case 0x2: /* NAND Flash (1.8V) */ > > + case 0x3: /* NAND Flash (3.0V) */ > > + return BOOT_DEVICE_NAND; > > + case 0x4: /* SD/MMC External Transceiver (1.8V) */ > > + case 0x5: /* SD/MMC Internal Transceiver (3.0V) */ > > + return BOOT_DEVICE_MMC1; > > + case 0x6: /* QSPI Flash (1.8V) */ > > + case 0x7: /* QSPI Flash (3.0V) */ > > + return BOOT_DEVICE_SPI; > > + default: > > + printf("Invalid boot device (bsel=%08x)!\n", > > bsel); > > + hang(); > > + } > > +#endif > > ?} > You missed my comment from V1: > > You should just do a shift define??here, so you don't have to add > all > this extra code here. Something like > > switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7) > Okay, noted. > > Dinh