[U-Boot] Some discussion about Allwinner DesignWare DRAM controller SPL code cleanup

[Icenowy Zheng <icenowy@aosc.xyz>]

Hi Jens, Andre, Chen-Yu and everyone,
As we know, allwinner start to refuse to provide code about DRAM initialization
after H3.
For A64, H5, V3s we have already did some work on reusing H3 code and it gives
good result.
For R40 the result is also usable (although half of the memory is lost)
I think we will need some refactor, which will makes the H3 driver finally a
SUNXI_DW_DRAM driver ;-)
The first thing I want to say is that the DDR timing parameters part needs a lot
refactor, for V3s' integrated DDR2, for SoPine's LPDDR3, etc...
What I think is to create some header files included by the DRAM driver which
defines the timing parameters, and make dram_sun8i_h3.c include them by the
choice in .config .
The second thing is that, for some alike controller from AW, we have at least
source files: dram_sun8i_{a33,h3}.c (A33 uses a similar DW DRAM).
Should we merge A33 into the H3 source code?
Opinions wanted ;-)

Thanks,
Icenowy