[U-Boot] [PATCH v4 3/9] ARM: stm32: cleanup stm32f7 files

Vikas MANOCHA
2017-01-24T19:35:20Z

Hi,

> -----Original Message-----
> From: Michael Kurz [mailto:michi.kurz at gmail.com]
> Sent: Sunday, January 22, 2017 7:04 AM
> To: u-boot at lists.denx.de
> Cc: Michael Kurz <michi.kurz@gmail.com>; Vikas MANOCHA <vikas.manocha@st.com>; Albert Aribaud
> <albert.u.boot@aribaud.net>; Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>; Joe Hershberger <joe.hershberger@ni.com>
> Subject: [PATCH v4 3/9] ARM: stm32: cleanup stm32f7 files
>
> Cleanup stm32f7 files:
> - use BIT macro
> - use GENMASK macro
> - use rcc struct instead of macro additions
>
> Add missing stm32f7 register in rcc struct
>
> Signed-off-by: Michael Kurz <michi.kurz@gmail.com>

Acked-by: Vikas MANOCHA<vikas.manocha@st.com>

Cheers,
Vikas

>
> ---
>
> Changes in v4:
> - Split struct stm32_rcc_regs into two structs (common and stm32f7 specific)
>
> Changes in v3:
> - Removed 'prefix all constants with STM32_'
> - Reverted move of header into source file (rcc.h -> clock.c)
>
> Changes in v2:
> - Add cleanup patch
>
> arch/arm/include/asm/arch-stm32f7/fmc.h | 6 +-
> arch/arm/include/asm/arch-stm32f7/gpt.h | 6 +-
> arch/arm/include/asm/arch-stm32f7/rcc.h | 50 ++++++----
> arch/arm/include/asm/arch-stm32f7/stm32.h | 12 ++-
> arch/arm/mach-stm32/stm32f7/clock.c | 154 ++++++++++++-----------------
> board/st/stm32f746-disco/stm32f746-disco.c | 7 +-
> 6 files changed, 111 insertions(+), 124 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-stm32f7/fmc.h b/arch/arm/include/asm/arch-stm32f7/fmc.h
> index 7dd5077..d61a86f 100644
> --- a/arch/arm/include/asm/arch-stm32f7/fmc.h
> +++ b/arch/arm/include/asm/arch-stm32f7/fmc.h
> @@ -58,12 +58,12 @@ struct stm32_fmc_regs {
> #define FMC_SDCMR_MODE_SELFREFRESH 5
> #define FMC_SDCMR_MODE_POWERDOWN 6
>
> -#define FMC_SDCMR_BANK_1 (1 << 4)
> -#define FMC_SDCMR_BANK_2 (1 << 3)
> +#define FMC_SDCMR_BANK_1 BIT(4)
> +#define FMC_SDCMR_BANK_2 BIT(3)
>
> #define FMC_SDCMR_MODE_REGISTER_SHIFT 9
>
> -#define FMC_SDSR_BUSY (1 << 5)
> +#define FMC_SDSR_BUSY BIT(5)
>
> #define FMC_BUSY_WAIT() do { \
> __asm__ __volatile__ ("dsb" : : : "memory"); \ diff --git a/arch/arm/include/asm/arch-stm32f7/gpt.h
> b/arch/arm/include/asm/arch-stm32f7/gpt.h
> index 903bdf6..e9e0c14 100644
> --- a/arch/arm/include/asm/arch-stm32f7/gpt.h
> +++ b/arch/arm/include/asm/arch-stm32f7/gpt.h
> @@ -38,8 +38,8 @@ struct gpt_regs *const gpt1_regs_ptr =
> (struct gpt_regs *)TIM2_BASE;
>
> /* Timer control1 register */
> -#define GPT_CR1_CEN 0x0001
> -#define GPT_MODE_AUTO_RELOAD (1 << 7)
> +#define GPT_CR1_CEN BIT(0)
> +#define GPT_MODE_AUTO_RELOAD BIT(7)
>
> /* Auto reload register for free running config */
> #define GPT_FREE_RUNNING 0xFFFFFFFF
> @@ -48,6 +48,6 @@ struct gpt_regs *const gpt1_regs_ptr =
> #define CONFIG_STM32_HZ 1000
>
> /* Timer Event Generation registers */
> -#define TIM_EGR_UG (1 << 0)
> +#define TIM_EGR_UG BIT(0)
>
> #endif
> diff --git a/arch/arm/include/asm/arch-stm32f7/rcc.h b/arch/arm/include/asm/arch-stm32f7/rcc.h
> index 8bfb7b6..184c366 100644
> --- a/arch/arm/include/asm/arch-stm32f7/rcc.h
> +++ b/arch/arm/include/asm/arch-stm32f7/rcc.h
> @@ -34,31 +34,43 @@
> #define RCC_PLLSAICFG 0x88 /* PLLSAI configuration */
> #define RCC_DCKCFG1 0x8C /* dedicated clocks configuration register */
> #define RCC_DCKCFG2 0x90 /* dedicated clocks configuration register */
> +/*
> + * RCC AHB1ENR specific definitions
> + */
> +#define RCC_AHB1ENR_GPIO_A_EN BIT(0)
> +#define RCC_AHB1ENR_GPIO_B_EN BIT(1)
> +#define RCC_AHB1ENR_GPIO_C_EN BIT(2)
> +#define RCC_AHB1ENR_GPIO_D_EN BIT(3)
> +#define RCC_AHB1ENR_GPIO_E_EN BIT(4)
> +#define RCC_AHB1ENR_GPIO_F_EN BIT(5)
> +#define RCC_AHB1ENR_GPIO_G_EN BIT(6)
> +#define RCC_AHB1ENR_GPIO_H_EN BIT(7)
> +#define RCC_AHB1ENR_GPIO_I_EN BIT(8)
> +#define RCC_AHB1ENR_GPIO_J_EN BIT(9)
> +#define RCC_AHB1ENR_GPIO_K_EN BIT(10)
> +#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
> +#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
> +#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
> +#define RCC_AHB1ENR_ETHMAC_PTP_EN BIT(28)
>
> -#define RCC_APB1ENR_TIM2EN (1 << 0)
> -#define RCC_APB1ENR_PWREN (1 << 28)
> +/*
> + * RCC AHB3ENR specific definitions
> + */
> +#define RCC_AHB3ENR_FMC_EN BIT(0)
>
> /*
> - * RCC USART specific definitions
> + * RCC APB1ENR specific definitions
> */
> -#define RCC_ENR_USART1EN (1 << 4)
> -#define RCC_ENR_USART2EN (1 << 17)
> -#define RCC_ENR_USART3EN (1 << 18)
> -#define RCC_ENR_USART6EN (1 << 5)
> +#define RCC_APB1ENR_TIM2EN BIT(0)
> +#define RCC_APB1ENR_USART2EN BIT(17)
> +#define RCC_APB1ENR_USART3EN BIT(18)
> +#define RCC_APB1ENR_PWREN BIT(28)
>
> /*
> - * RCC GPIO specific definitions
> + * RCC APB2ENR specific definitions
> */
> -#define RCC_ENR_GPIO_A_EN (1 << 0)
> -#define RCC_ENR_GPIO_B_EN (1 << 1)
> -#define RCC_ENR_GPIO_C_EN (1 << 2)
> -#define RCC_ENR_GPIO_D_EN (1 << 3)
> -#define RCC_ENR_GPIO_E_EN (1 << 4)
> -#define RCC_ENR_GPIO_F_EN (1 << 5)
> -#define RCC_ENR_GPIO_G_EN (1 << 6)
> -#define RCC_ENR_GPIO_H_EN (1 << 7)
> -#define RCC_ENR_GPIO_I_EN (1 << 8)
> -#define RCC_ENR_GPIO_J_EN (1 << 9)
> -#define RCC_ENR_GPIO_K_EN (1 << 10)
> +#define RCC_APB2ENR_USART1EN BIT(4)
> +#define RCC_APB2ENR_USART6EN BIT(5)
> +#define RCC_APB2ENR_SYSCFGEN BIT(14)
>
> #endif
> diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h
> index de55ae5..a425178 100644
> --- a/arch/arm/include/asm/arch-stm32f7/stm32.h
> +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h
> @@ -32,6 +32,7 @@
>
> #define USART1_BASE (APB2_PERIPH_BASE + 0x1000)
> #define USART6_BASE (APB2_PERIPH_BASE + 0x1400)
> +#define STM32_SYSCFG_BASE (APB2_PERIPH_BASE + 0x3800)
>
> #define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000)
> #define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400)
> @@ -62,7 +63,7 @@ enum clock {
> CLOCK_APB1,
> CLOCK_APB2
> };
> -#define STM32_BUS_MASK 0xFFFF0000
> +#define STM32_BUS_MASK GENMASK(31, 16)
>
> struct stm32_rcc_regs {
> u32 cr; /* RCC clock control */
> @@ -95,11 +96,16 @@ struct stm32_rcc_regs {
> u32 rsv6[2];
> u32 sscgr; /* RCC spread spectrum clock generation */
> u32 plli2scfgr; /* RCC PLLI2S configuration */
> - u32 pllsaicfgr;
> - u32 dckcfgr;
> + u32 pllsaicfgr; /* PLLSAI configuration */
> + u32 dckcfgr; /* dedicated clocks configuration register */
> };
> #define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
>
> +struct stm32_rcc_ext_f7_regs {
> + u32 dckcfgr2; /* dedicated clocks configuration register */
> +};
> +#define STM32_RCC_EXT_F7 ((struct stm32_rcc_ext_f7_regs *) (RCC_BASE + sizeof(struct stm32_rcc_regs)))
> +
> struct stm32_pwr_regs {
> u32 cr1; /* power control register 1 */
> u32 csr1; /* power control/status register 2 */ diff --git a/arch/arm/mach-stm32/stm32f7/clock.c b/arch/arm/mach-
> stm32/stm32f7/clock.c
> index 78d22d4..8091c74 100644
> --- a/arch/arm/mach-stm32/stm32f7/clock.c
> +++ b/arch/arm/mach-stm32/stm32f7/clock.c
> @@ -11,76 +11,50 @@
> #include <asm/arch/stm32.h>
> #include <asm/arch/stm32_periph.h>
>
> -#define RCC_CR_HSION (1 << 0)
> -#define RCC_CR_HSEON (1 << 16)
> -#define RCC_CR_HSERDY (1 << 17)
> -#define RCC_CR_HSEBYP (1 << 18)
> -#define RCC_CR_CSSON (1 << 19)
> -#define RCC_CR_PLLON (1 << 24)
> -#define RCC_CR_PLLRDY (1 << 25)
> +#define RCC_CR_HSION BIT(0)
> +#define RCC_CR_HSEON BIT(16)
> +#define RCC_CR_HSERDY BIT(17)
> +#define RCC_CR_HSEBYP BIT(18)
> +#define RCC_CR_CSSON BIT(19)
> +#define RCC_CR_PLLON BIT(24)
> +#define RCC_CR_PLLRDY BIT(25)
>
> -#define RCC_PLLCFGR_PLLM_MASK 0x3F
> -#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
> -#define RCC_PLLCFGR_PLLP_MASK 0x30000
> -#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
> -#define RCC_PLLCFGR_PLLSRC (1 << 22)
> -#define RCC_PLLCFGR_PLLM_SHIFT 0
> -#define RCC_PLLCFGR_PLLN_SHIFT 6
> -#define RCC_PLLCFGR_PLLP_SHIFT 16
> -#define RCC_PLLCFGR_PLLQ_SHIFT 24
> +#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
> +#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
> +#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
> +#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
> +#define RCC_PLLCFGR_PLLSRC BIT(22)
> +#define RCC_PLLCFGR_PLLM_SHIFT 0
> +#define RCC_PLLCFGR_PLLN_SHIFT 6
> +#define RCC_PLLCFGR_PLLP_SHIFT 16
> +#define RCC_PLLCFGR_PLLQ_SHIFT 24
>
> -#define RCC_CFGR_AHB_PSC_MASK 0xF0
> -#define RCC_CFGR_APB1_PSC_MASK 0x1C00
> -#define RCC_CFGR_APB2_PSC_MASK 0xE000
> -#define RCC_CFGR_SW0 (1 << 0)
> -#define RCC_CFGR_SW1 (1 << 1)
> -#define RCC_CFGR_SW_MASK 0x3
> -#define RCC_CFGR_SW_HSI 0
> -#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
> -#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
> -#define RCC_CFGR_SWS0 (1 << 2)
> -#define RCC_CFGR_SWS1 (1 << 3)
> -#define RCC_CFGR_SWS_MASK 0xC
> -#define RCC_CFGR_SWS_HSI 0
> -#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
> -#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
> -#define RCC_CFGR_HPRE_SHIFT 4
> -#define RCC_CFGR_PPRE1_SHIFT 10
> -#define RCC_CFGR_PPRE2_SHIFT 13
> -
> -#define RCC_APB1ENR_PWREN (1 << 28)
> -
> -/*
> - * RCC USART specific definitions
> - */
> -#define RCC_ENR_USART1EN (1 << 4)
> -#define RCC_ENR_USART2EN (1 << 17)
> -#define RCC_ENR_USART3EN (1 << 18)
> -#define RCC_ENR_USART6EN (1 << 5)
> +#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
> +#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
> +#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
> +#define RCC_CFGR_SW0 BIT(0)
> +#define RCC_CFGR_SW1 BIT(1)
> +#define RCC_CFGR_SW_MASK GENMASK(1, 0)
> +#define RCC_CFGR_SW_HSI 0
> +#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
> +#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
> +#define RCC_CFGR_SWS0 BIT(2)
> +#define RCC_CFGR_SWS1 BIT(3)
> +#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
> +#define RCC_CFGR_SWS_HSI 0
> +#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
> +#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
> +#define RCC_CFGR_HPRE_SHIFT 4
> +#define RCC_CFGR_PPRE1_SHIFT 10
> +#define RCC_CFGR_PPRE2_SHIFT 13
>
> /*
> * Offsets of some PWR registers
> */
> -#define PWR_CR1_ODEN (1 << 16)
> -#define PWR_CR1_ODSWEN (1 << 17)
> -#define PWR_CSR1_ODRDY (1 << 16)
> -#define PWR_CSR1_ODSWRDY (1 << 17)
> -
> -
> -/*
> - * RCC GPIO specific definitions
> - */
> -#define RCC_ENR_GPIO_A_EN (1 << 0)
> -#define RCC_ENR_GPIO_B_EN (1 << 1)
> -#define RCC_ENR_GPIO_C_EN (1 << 2)
> -#define RCC_ENR_GPIO_D_EN (1 << 3)
> -#define RCC_ENR_GPIO_E_EN (1 << 4)
> -#define RCC_ENR_GPIO_F_EN (1 << 5)
> -#define RCC_ENR_GPIO_G_EN (1 << 6)
> -#define RCC_ENR_GPIO_H_EN (1 << 7)
> -#define RCC_ENR_GPIO_I_EN (1 << 8)
> -#define RCC_ENR_GPIO_J_EN (1 << 9)
> -#define RCC_ENR_GPIO_K_EN (1 << 10)
> +#define PWR_CR1_ODEN BIT(16)
> +#define PWR_CR1_ODSWEN BIT(17)
> +#define PWR_CSR1_ODRDY BIT(16)
> +#define PWR_CSR1_ODSWRDY BIT(17)
>
> struct pll_psc {
> u8 pll_m;
> @@ -92,21 +66,21 @@ struct pll_psc {
> u8 apb2_psc;
> };
>
> -#define AHB_PSC_1 0
> -#define AHB_PSC_2 0x8
> -#define AHB_PSC_4 0x9
> -#define AHB_PSC_8 0xA
> -#define AHB_PSC_16 0xB
> -#define AHB_PSC_64 0xC
> -#define AHB_PSC_128 0xD
> -#define AHB_PSC_256 0xE
> -#define AHB_PSC_512 0xF
> +#define AHB_PSC_1 0
> +#define AHB_PSC_2 0x8
> +#define AHB_PSC_4 0x9
> +#define AHB_PSC_8 0xA
> +#define AHB_PSC_16 0xB
> +#define AHB_PSC_64 0xC
> +#define AHB_PSC_128 0xD
> +#define AHB_PSC_256 0xE
> +#define AHB_PSC_512 0xF
>
> -#define APB_PSC_1 0
> -#define APB_PSC_2 0x4
> -#define APB_PSC_4 0x5
> -#define APB_PSC_8 0x6
> -#define APB_PSC_16 0x7
> +#define APB_PSC_1 0
> +#define APB_PSC_2 0x4
> +#define APB_PSC_4 0x5
> +#define APB_PSC_8 0x6
> +#define APB_PSC_16 0x7
>
> #if !defined(CONFIG_STM32_HSE_HZ)
> #error "CONFIG_STM32_HSE_HZ not defined!"
> @@ -243,40 +217,40 @@ void clock_setup(int peripheral) {
> switch (peripheral) {
> case USART1_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_APB2ENR, RCC_ENR_USART1EN);
> + setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
> break;
> case GPIO_A_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_A_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
> break;
> case GPIO_B_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_B_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
> break;
> case GPIO_C_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_C_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
> break;
> case GPIO_D_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_D_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
> break;
> case GPIO_E_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_E_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
> break;
> case GPIO_F_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_F_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
> break;
> case GPIO_G_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_G_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
> break;
> case GPIO_H_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_H_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
> break;
> case GPIO_I_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_I_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
> break;
> case GPIO_J_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_J_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
> break;
> case GPIO_K_CLOCK_CFG:
> - setbits_le32(RCC_BASE + RCC_AHB1ENR, RCC_ENR_GPIO_K_EN);
> + setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
> break;
> default:
> break;
> diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c
> index 404fdfa..c769da0 100644
> --- a/board/st/stm32f746-disco/stm32f746-disco.c
> +++ b/board/st/stm32f746-disco/stm32f746-disco.c
> @@ -114,11 +114,6 @@ out:
> return rv;
> }
>
> -/*
> - * STM32 RCC FMC specific definitions
> - */
> -#define RCC_ENR_FMC (1 << 0) /* FMC module clock */
> -
> static inline u32 _ns2clk(u32 ns, u32 freq) {
> u32 tmp = freq/1000000;
> @@ -176,7 +171,7 @@ int dram_init(void)
> if (rv)
> return rv;
>
> - setbits_le32(RCC_BASE + RCC_AHB3ENR, RCC_ENR_FMC);
> + setbits_le32(&STM32_RCC->ahb3enr, RCC_AHB3ENR_FMC_EN);
>
> /*
> * Get frequency for NS2CLK calculation.
> --
> 2.1.4