From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chin Liang See Date: Wed, 15 Feb 2017 13:56:05 +0700 Subject: [U-Boot] [PATCH v2] arm: socfpga: fix issue with warm reset when CSEL is 0 In-Reply-To: <1487096912-18457-1-git-send-email-dwesterg@gmail.com> References: <1487096912-18457-1-git-send-email-dwesterg@gmail.com> Message-ID: <1487141765.1901.0.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Sel, 2017-02-14 at 10:28 -0800, Dalon Westergreen wrote: > When CSEL=0x0 the socfpga bootrom does not touch the clock > configuration for the device.??This can lead to a boot failure > on warm resets.??To address this, the bootrom is configured to > run a bit of code in the last 4KB of onchip ram on a warm reset. > This code puts the PLLs in bypass, disables the bootrom configuration > to run the code snippet, and issues a warm reset to run the bootrom. > > Signed-off-by: Dalon Westergreen > > -- > Changes in V2: > ?- Fix checkpatch issues predominently due to whitespace issues > --- > ?arch/arm/mach-socfpga/Makefile?????????????????????|??2 +- > ?arch/arm/mach-socfpga/include/mach/clock_manager.h | 26 +++++++- > ?arch/arm/mach-socfpga/include/mach/reset_manager.h |??4 ++ > ?.../arm/mach-socfpga/include/mach/system_manager.h |??7 ++- > ?arch/arm/mach-socfpga/misc.c???????????????????????| 27 ++++++++ > ?arch/arm/mach-socfpga/reset_clock_manager.S????????| 71 > ++++++++++++++++++++++ > ?6 files changed, 134 insertions(+), 3 deletions(-) > ?create mode 100644 arch/arm/mach-socfpga/reset_clock_manager.S > > Acked-by: Chin Liang See Thanks Chin Liang