[U-Boot] [PATCH v2] armv8: fsl-lsch3: Instantiate TZASC configuration in 2 groups

[Ashish Kumar <Ashish.Kumar@nxp.com>]

 Number of TZASC instances may vary across NXP SoCs.
 So put TZASC configuration under instance specific defines.

Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
---
v2:
 Change description to make it more appropriate

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig    |  8 ++++++++
 arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 24 +++++++++++++-----------
 2 files changed, 21 insertions(+), 11 deletions(-)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 29bc756..9eaafba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -62,6 +62,8 @@ config ARCH_LS2080A
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
 	select SYS_FSL_SRDS_2
+	select FSL_TZASC_1
+	select FSL_TZASC_2
 	select SYS_FSL_ERRATUM_A008336
 	select SYS_FSL_ERRATUM_A008511
 	select SYS_FSL_ERRATUM_A008514
@@ -201,6 +203,12 @@ config SYS_FSL_SRDS_2
 config SYS_HAS_SERDES
 	bool
 
+config FSL_TZASC_1
+	bool
+
+config FSL_TZASC_2
+	bool
+
 endmenu
 
 menu "Layerscape clock tree configuration"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index a2185f2..79d1637 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -229,38 +229,40 @@ ENTRY(lowlevel_init)
 	 * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
 	 * 	 placeholders.
 	 */
+#ifdef CONFIG_FSL_TZASC_1
 	ldr	x1, =TZASC_GATE_KEEPER(0)
 	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
 	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
 	str	w0, [x1]
 
-	ldr	x1, =TZASC_GATE_KEEPER(1)
-	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
-	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
-	str	w0, [x1]
-
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(0)
 	ldr	w0, [x1]		/* Region-0 Attributes Register */
 	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
 	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
 	str	w0, [x1]
 
+	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
+	ldr	w0, [x1]		/* Region-0 Access Register */
+	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
+	str	w0, [x1]
+#endif
+#ifdef CONFIG_FSL_TZASC_2
+	ldr	x1, =TZASC_GATE_KEEPER(1)
+	ldr	w0, [x1]		/* Filter 0 Gate Keeper Register */
+	orr	w0, w0, #1 << 0		/* Set open_request for Filter 0 */
+	str	w0, [x1]
+
 	ldr	x1, =TZASC_REGION_ATTRIBUTES_0(1)
 	ldr	w0, [x1]		/* Region-1 Attributes Register */
 	orr	w0, w0, #1 << 31	/* Set Sec global write en, Bit[31] */
 	orr	w0, w0, #1 << 30	/* Set Sec global read en, Bit[30] */
 	str	w0, [x1]
 
-	ldr	x1, =TZASC_REGION_ID_ACCESS_0(0)
-	ldr	w0, [x1]		/* Region-0 Access Register */
-	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
-	str	w0, [x1]
-
 	ldr	x1, =TZASC_REGION_ID_ACCESS_0(1)
 	ldr	w0, [x1]		/* Region-1 Attributes Register */
 	mov	w0, #0xFFFFFFFF		/* Set nsaid_wr_en and nsaid_rd_en */
 	str	w0, [x1]
-
+#endif
 	isb
 	dsb	sy
 #endif
-- 
1.9.1