* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-03 12:50 [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee Tien Fong
@ 2017-03-03 12:50 ` Chee Tien Fong
2017-03-03 14:50 ` Dinh Nguyen
2017-03-05 0:57 ` Marek Vasut
2017-03-03 12:50 ` [U-Boot] [PATCH 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 Chee Tien Fong
` (3 subsequent siblings)
4 siblings, 2 replies; 11+ messages in thread
From: Chee Tien Fong @ 2017-03-03 12:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch removes the unused passing parameter of socfpga_bridges_reset
function in Arria10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ching Liang See <chin.liang.see@intel.com>
Cc: Ley Foon <ley.foon.tan@intel.com>
Cc: Westergreen Dalon <dalon.westergreen@intel.com>
---
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ---
.../include/mach/reset_manager_arria10.h | 1 +
.../mach-socfpga/include/mach/reset_manager_gen5.h | 1 +
arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
4 files changed, 3 insertions(+), 4 deletions(-)
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
index 64526b6..f5189e8 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
@@ -8,9 +8,6 @@
#define _RESET_MANAGER_H_
void reset_cpu(ulong addr);
-
-void socfpga_bridges_reset(int enable);
-
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
old mode 100755
new mode 100644
index 2668a86..954381c
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -16,6 +16,7 @@ void reset_assert_fpga_connected_peripherals(void);
void reset_deassert_osc1wd0(void);
void reset_assert_uart(void);
void reset_deassert_uart(void);
+void socfpga_bridges_reset(void);
struct socfpga_reset_manager {
u32 stat;
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
old mode 100755
new mode 100644
index 028974a..da17f4c
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
@@ -8,6 +8,7 @@
#define _RESET_MANAGER_GEN5_H_
void reset_deassert_peripherals_handoff(void);
+void socfpga_bridges_reset(int enable);
struct socfpga_reset_manager {
u32 status;
diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
index 01156de..684c6be 100644
--- a/arch/arm/mach-socfpga/reset_manager_arria10.c
+++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
@@ -355,7 +355,7 @@ void socfpga_bridges_reset(int enable)
/* For SoCFPGA-VT, this is NOP. */
}
#else
-void socfpga_bridges_reset(int enable)
+void socfpga_bridges_reset(void)
{
/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) */
/* set idle request to all bridges */
--
1.7.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-03 12:50 ` [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset Chee Tien Fong
@ 2017-03-03 14:50 ` Dinh Nguyen
2017-03-05 0:57 ` Marek Vasut
1 sibling, 0 replies; 11+ messages in thread
From: Dinh Nguyen @ 2017-03-03 14:50 UTC (permalink / raw)
To: u-boot
On 03/03/2017 06:50 AM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This patch removes the unused passing parameter of socfpga_bridges_reset
> function in Arria10.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ching Liang See <chin.liang.see@intel.com>
> Cc: Ley Foon <ley.foon.tan@intel.com>
> Cc: Westergreen Dalon <dalon.westergreen@intel.com>
> ---
Can you please add the proper [U-Boot][PATCH] header to your patches? It
would really help with filters for all of us!
Thanks,
Dinh
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-03 12:50 ` [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset Chee Tien Fong
2017-03-03 14:50 ` Dinh Nguyen
@ 2017-03-05 0:57 ` Marek Vasut
2017-03-06 4:45 ` Chee, Tien Fong
1 sibling, 1 reply; 11+ messages in thread
From: Marek Vasut @ 2017-03-05 0:57 UTC (permalink / raw)
To: u-boot
On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This patch removes the unused passing parameter of socfpga_bridges_reset
> function in Arria10.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Cc: Marek Vasut <marex@denx.de>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ching Liang See <chin.liang.see@intel.com>
> Cc: Ley Foon <ley.foon.tan@intel.com>
> Cc: Westergreen Dalon <dalon.westergreen@intel.com>
We do NOT have arria10 support in mainline, I am confused.
Can you please sync with Ley when submitting patches ?
Thanks
> ---
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ---
> .../include/mach/reset_manager_arria10.h | 1 +
> .../mach-socfpga/include/mach/reset_manager_gen5.h | 1 +
> arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
> 4 files changed, 3 insertions(+), 4 deletions(-)
> mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> mode change 100755 => 100644 arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> index 64526b6..f5189e8 100644
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> @@ -8,9 +8,6 @@
> #define _RESET_MANAGER_H_
>
> void reset_cpu(ulong addr);
> -
> -void socfpga_bridges_reset(int enable);
> -
> void socfpga_per_reset(u32 reset, int set);
> void socfpga_per_reset_all(void);
>
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> old mode 100755
> new mode 100644
> index 2668a86..954381c
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> @@ -16,6 +16,7 @@ void reset_assert_fpga_connected_peripherals(void);
> void reset_deassert_osc1wd0(void);
> void reset_assert_uart(void);
> void reset_deassert_uart(void);
> +void socfpga_bridges_reset(void);
>
> struct socfpga_reset_manager {
> u32 stat;
> diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> old mode 100755
> new mode 100644
> index 028974a..da17f4c
> --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> @@ -8,6 +8,7 @@
> #define _RESET_MANAGER_GEN5_H_
>
> void reset_deassert_peripherals_handoff(void);
> +void socfpga_bridges_reset(int enable);
>
> struct socfpga_reset_manager {
> u32 status;
> diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c b/arch/arm/mach-socfpga/reset_manager_arria10.c
> index 01156de..684c6be 100644
> --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> @@ -355,7 +355,7 @@ void socfpga_bridges_reset(int enable)
> /* For SoCFPGA-VT, this is NOP. */
> }
> #else
> -void socfpga_bridges_reset(int enable)
> +void socfpga_bridges_reset(void)
> {
> /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) */
> /* set idle request to all bridges */
>
^ permalink raw reply [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-05 0:57 ` Marek Vasut
@ 2017-03-06 4:45 ` Chee, Tien Fong
2017-03-07 3:45 ` Marek Vasut
0 siblings, 1 reply; 11+ messages in thread
From: Chee, Tien Fong @ 2017-03-06 4:45 UTC (permalink / raw)
To: u-boot
On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > This patch removes the unused passing parameter of
> > socfpga_bridges_reset
> > function in Arria10.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > Cc: Marek Vasut <marex@denx.de>
> > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > Cc: Ching Liang See <chin.liang.see@intel.com>
> > Cc: Ley Foon <ley.foon.tan@intel.com>
> > Cc: Westergreen Dalon <dalon.westergreen@intel.com>
> We do NOT have arria10 support in mainline, I am confused.
> Can you please sync with Ley when submitting patches ?
>
> Thanks
>
This series is working on top of [1] initial patchset which enables
the basic support for Arria 10 and other features.
https://www.mail-archive.com/u-boot at lists.denx.de/msg240053.html
I just realized i forgot to +CC you guys in the cover letter,
https://www.mail-archive.com/u-boot at lists.denx.de/msg240829.html.
I am sorry to have you confused.
> >
> > ---
> > arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 ---
> > .../include/mach/reset_manager_arria10.h | 1 +
> > .../mach-socfpga/include/mach/reset_manager_gen5.h | 1 +
> > arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
> > 4 files changed, 3 insertions(+), 4 deletions(-)
> > mode change 100755 => 100644 arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> > mode change 100755 => 100644 arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h
> >
> > diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > index 64526b6..f5189e8 100644
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h
> > @@ -8,9 +8,6 @@
> > #define _RESET_MANAGER_H_
> >
> > void reset_cpu(ulong addr);
> > -
> > -void socfpga_bridges_reset(int enable);
> > -
> > void socfpga_per_reset(u32 reset, int set);
> > void socfpga_per_reset_all(void);
> >
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_arria10.h
> > old mode 100755
> > new mode 100644
> > index 2668a86..954381c
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
> > @@ -16,6 +16,7 @@ void
> > reset_assert_fpga_connected_peripherals(void);
> > void reset_deassert_osc1wd0(void);
> > void reset_assert_uart(void);
> > void reset_deassert_uart(void);
> > +void socfpga_bridges_reset(void);
> >
> > struct socfpga_reset_manager {
> > u32 stat;
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h b/arch/arm/mach-
> > socfpga/include/mach/reset_manager_gen5.h
> > old mode 100755
> > new mode 100644
> > index 028974a..da17f4c
> > --- a/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_gen5.h
> > @@ -8,6 +8,7 @@
> > #define _RESET_MANAGER_GEN5_H_
> >
> > void reset_deassert_peripherals_handoff(void);
> > +void socfpga_bridges_reset(int enable);
> >
> > struct socfpga_reset_manager {
> > u32 status;
> > diff --git a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > index 01156de..684c6be 100644
> > --- a/arch/arm/mach-socfpga/reset_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/reset_manager_arria10.c
> > @@ -355,7 +355,7 @@ void socfpga_bridges_reset(int enable)
> > /* For SoCFPGA-VT, this is NOP. */
> > }
> > #else
> > -void socfpga_bridges_reset(int enable)
> > +void socfpga_bridges_reset(void)
> > {
> > /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
> > fpga2sdram) */
> > /* set idle request to all bridges */
> >
^ permalink raw reply [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-06 4:45 ` Chee, Tien Fong
@ 2017-03-07 3:45 ` Marek Vasut
2017-03-07 9:11 ` Chee, Tien Fong
0 siblings, 1 reply; 11+ messages in thread
From: Marek Vasut @ 2017-03-07 3:45 UTC (permalink / raw)
To: u-boot
On 03/06/2017 05:45 AM, Chee, Tien Fong wrote:
> On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
>> On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.chee@intel.com>
>>>
>>> This patch removes the unused passing parameter of
>>> socfpga_bridges_reset
>>> function in Arria10.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>>> Cc: Marek Vasut <marex@denx.de>
>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>> Cc: Ching Liang See <chin.liang.see@intel.com>
>>> Cc: Ley Foon <ley.foon.tan@intel.com>
>>> Cc: Westergreen Dalon <dalon.westergreen@intel.com>
>> We do NOT have arria10 support in mainline, I am confused.
>> Can you please sync with Ley when submitting patches ?
>>
>> Thanks
>>
> This series is working on top of [1] initial patchset which enables
> the basic support for Arria 10 and other features.
> https://www.mail-archive.com/u-boot at lists.denx.de/msg240053.html
This patchset is still work-in-progress. Sending patches on top of it is
completely useless . Please work with Ley and integrate them or wait
until the initial patchset lands.
> I just realized i forgot to +CC you guys in the cover letter,
> https://www.mail-archive.com/u-boot at lists.denx.de/msg240829.html.
> I am sorry to have you confused.
[...]
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset
2017-03-07 3:45 ` Marek Vasut
@ 2017-03-07 9:11 ` Chee, Tien Fong
0 siblings, 0 replies; 11+ messages in thread
From: Chee, Tien Fong @ 2017-03-07 9:11 UTC (permalink / raw)
To: u-boot
On Sel, 2017-03-07 at 04:45 +0100, Marek Vasut wrote:
> On 03/06/2017 05:45 AM, Chee, Tien Fong wrote:
> >
> > On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
> > >
> > > On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > This patch removes the unused passing parameter of
> > > > socfpga_bridges_reset
> > > > function in Arria10.
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > Cc: Marek Vasut <marex@denx.de>
> > > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > > Cc: Ching Liang See <chin.liang.see@intel.com>
> > > > Cc: Ley Foon <ley.foon.tan@intel.com>
> > > > Cc: Westergreen Dalon <dalon.westergreen@intel.com>
> > > We do NOT have arria10 support in mainline, I am confused.
> > > Can you please sync with Ley when submitting patches ?
> > >
> > > Thanks
> > >
> > This series is working on top of [1] initial patchset which enables
> > the basic support for Arria 10 and other features.
> > https://www.mail-archive.com/u-boot at lists.denx.de/msg240053.html
> This patchset is still work-in-progress. Sending patches on top of it
> is
> completely useless . Please work with Ley and integrate them or wait
> until the initial patchset lands.
>
Okay.
> >
> > I just realized i forgot to +CC you guys in the cover letter,
> > https://www.mail-archive.com/u-boot at lists.denx.de/msg240829.html.
> > I am sorry to have you confused.
> [...]
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10.
2017-03-03 12:50 [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee Tien Fong
2017-03-03 12:50 ` [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset Chee Tien Fong
@ 2017-03-03 12:50 ` Chee Tien Fong
2017-03-03 12:50 ` [U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver Chee Tien Fong
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Chee Tien Fong @ 2017-03-03 12:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Move the Gen5 specific code to gen5 files. No functional change.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ching Liang See <chin.liang.see@intel.com>
Cc: Ley Foon <ley.foon.tan@intel.com>
Cc: Westergreen Dalon <dalon.westergreen@intel.com>
---
arch/arm/mach-socfpga/Makefile | 2 +-
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 68 +----
.../mach/{fpga_manager.h => fpga_manager_gen5.h} | 66 +++---
drivers/fpga/Makefile | 5 +-
drivers/fpga/socfpga.c | 272 +-------------------
drivers/fpga/{socfpga.c => socfpga_gen5.c} | 33 +---
6 files changed, 51 insertions(+), 395 deletions(-)
copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (85%)
copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (91%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 7c7b471..901bf91 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,7 +9,6 @@
obj-y += board.o
obj-y += clock_manager.o
-obj-y += fpga_manager.o
obj-y += misc.o
obj-y += reset_manager.o
obj-y += timer.o
@@ -28,6 +27,7 @@ obj-y += reset_manager_gen5.o
obj-y += scan_manager.o
obj-y += system_manager_gen5.o
obj-y += wrap_pll_config.o
+obj-y += fpga_manager.o
endif
ifdef CONFIG_SPL_BUILD
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index a077e22..76a9289 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -10,58 +10,9 @@
#include <altera.h>
-struct socfpga_fpga_manager {
- /* FPGA Manager Module */
- u32 stat; /* 0x00 */
- u32 ctrl;
- u32 dclkcnt;
- u32 dclkstat;
- u32 gpo; /* 0x10 */
- u32 gpi;
- u32 misci; /* 0x18 */
- u32 _pad_0x1c_0x82c[517];
-
- /* Configuration Monitor (MON) Registers */
- u32 gpio_inten; /* 0x830 */
- u32 gpio_intmask;
- u32 gpio_inttype_level;
- u32 gpio_int_polarity;
- u32 gpio_intstatus; /* 0x840 */
- u32 gpio_raw_intstatus;
- u32 _pad_0x848;
- u32 gpio_porta_eoi;
- u32 gpio_ext_porta; /* 0x850 */
- u32 _pad_0x854_0x85c[3];
- u32 gpio_1s_sync; /* 0x860 */
- u32 _pad_0x864_0x868[2];
- u32 gpio_ver_id_code;
- u32 gpio_config_reg2; /* 0x870 */
- u32 gpio_config_reg1;
-};
-
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#include <asm/arch/fpga_manager_gen5.h>
+#endif
/* FPGA CD Ratio Value */
#define CDRATIO_x1 0x0
@@ -69,9 +20,12 @@ struct socfpga_fpga_manager {
#define CDRATIO_x4 0x2
#define CDRATIO_x8 0x3
-/* SoCFPGA support functions */
-int fpgamgr_test_fpga_ready(void);
-int fpgamgr_poll_fpga_ready(void);
-int fpgamgr_get_mode(void);
+#define FPGA_TIMEOUT_CNT 0x1000000
+
+#ifndef __ASSEMBLY__
+
+/* Common prototypes */
+int fpgamgr_dclkcnt_set(unsigned long cnt);
+#endif /* __ASSEMBLY__ */
#endif /* _FPGA_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
similarity index 85%
copy from arch/arm/mach-socfpga/include/mach/fpga_manager.h
copy to arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
index a077e22..c03566e 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_gen5.h
@@ -1,14 +1,38 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef _FPGA_MANAGER_H_
-#define _FPGA_MANAGER_H_
+#ifndef _FPGA_MANAGER_GEN5_H_
+#define _FPGA_MANAGER_GEN5_H_
-#include <altera.h>
+#define FPGAMGRREGS_STAT_MODE_MASK 0x7
+#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
+#define FPGAMGRREGS_STAT_MSEL_LSB 3
+
+#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
+#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
+#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
+#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
+#define FPGAMGRREGS_CTRL_EN_MASK 0x1
+#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
+
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
+#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
+
+/* FPGA Mode */
+#define FPGAMGRREGS_MODE_FPGAOFF 0x0
+#define FPGAMGRREGS_MODE_RESETPHASE 0x1
+#define FPGAMGRREGS_MODE_CFGPHASE 0x2
+#define FPGAMGRREGS_MODE_INITPHASE 0x3
+#define FPGAMGRREGS_MODE_USERMODE 0x4
+#define FPGAMGRREGS_MODE_UNKNOWN 0x5
+
+#ifndef __ASSEMBLY__
struct socfpga_fpga_manager {
/* FPGA Manager Module */
@@ -39,39 +63,11 @@ struct socfpga_fpga_manager {
u32 gpio_config_reg1;
};
-#define FPGAMGRREGS_STAT_MODE_MASK 0x7
-#define FPGAMGRREGS_STAT_MSEL_MASK 0xf8
-#define FPGAMGRREGS_STAT_MSEL_LSB 3
-
-#define FPGAMGRREGS_CTRL_CFGWDTH_MASK 0x200
-#define FPGAMGRREGS_CTRL_AXICFGEN_MASK 0x100
-#define FPGAMGRREGS_CTRL_NCONFIGPULL_MASK 0x4
-#define FPGAMGRREGS_CTRL_NCE_MASK 0x2
-#define FPGAMGRREGS_CTRL_EN_MASK 0x1
-#define FPGAMGRREGS_CTRL_CDRATIO_LSB 6
-
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CRC_MASK 0x8
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_ID_MASK 0x4
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK 0x2
-#define FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK 0x1
-
-/* FPGA Mode */
-#define FPGAMGRREGS_MODE_FPGAOFF 0x0
-#define FPGAMGRREGS_MODE_RESETPHASE 0x1
-#define FPGAMGRREGS_MODE_CFGPHASE 0x2
-#define FPGAMGRREGS_MODE_INITPHASE 0x3
-#define FPGAMGRREGS_MODE_USERMODE 0x4
-#define FPGAMGRREGS_MODE_UNKNOWN 0x5
-
-/* FPGA CD Ratio Value */
-#define CDRATIO_x1 0x0
-#define CDRATIO_x2 0x1
-#define CDRATIO_x4 0x2
-#define CDRATIO_x8 0x3
-
/* SoCFPGA support functions */
int fpgamgr_test_fpga_ready(void);
int fpgamgr_poll_fpga_ready(void);
int fpgamgr_get_mode(void);
-#endif /* _FPGA_MANAGER_H_ */
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_GEN5_H_ */
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index 777706f..c70ee40 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -19,5 +19,8 @@ obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
-obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+ifdef CONFIG_FPGA_SOCFPGA
+obj-y += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+endif
endif
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
index 3751574..8c2fdc1 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -15,24 +15,12 @@
DECLARE_GLOBAL_DATA_PTR;
/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
+#define FPGA_TIMEOUT_CNT 0x1000000
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
-static struct socfpga_system_manager *sysmgr_regs =
- (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-#endif
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
- clrsetbits_le32(&fpgamgr_regs->ctrl,
- 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
- (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}
-
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
+int fpgamgr_dclkcnt_set(unsigned long cnt)
{
unsigned long i;
@@ -54,257 +42,3 @@ static int fpgamgr_dclkcnt_set(unsigned long cnt)
return -ETIMEDOUT;
}
-
-/* Start the FPGA programming by initialize the FPGA Manager */
-static int fpgamgr_program_init(void)
-{
- unsigned long msel, i;
-
- /* Get the MSEL value */
- msel = readl(&fpgamgr_regs->stat);
- msel &= FPGAMGRREGS_STAT_MSEL_MASK;
- msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
-
- /*
- * Set the cfg width
- * If MSEL[3] = 1, cfg width = 32 bit
- */
- if (msel & 0x8) {
- setbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- /* MSEL[1:0] = 2, CD Ratio = 8 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x8);
-
- } else { /* MSEL[3] = 0 */
- clrbits_le32(&fpgamgr_regs->ctrl,
- FPGAMGRREGS_CTRL_CFGWDTH_MASK);
-
- /* To determine the CD ratio */
- /* MSEL[1:0] = 0, CD Ratio = 1 */
- if ((msel & 0x3) == 0x0)
- fpgamgr_set_cd_ratio(CDRATIO_x1);
- /* MSEL[1:0] = 1, CD Ratio = 2 */
- else if ((msel & 0x3) == 0x1)
- fpgamgr_set_cd_ratio(CDRATIO_x2);
- /* MSEL[1:0] = 2, CD Ratio = 4 */
- else if ((msel & 0x3) == 0x2)
- fpgamgr_set_cd_ratio(CDRATIO_x4);
- }
-
- /* To enable FPGA Manager configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
-
- /* To enable FPGA Manager drive over configuration line */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- /* Put FPGA into reset phase */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (1) wait until FPGA enter reset phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
- break;
- }
-
- /* If not in reset state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
- puts("FPGA: Could not reset\n");
- return -1;
- }
-
- /* Release FPGA from reset phase */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
-
- /* (2) wait until FPGA enter configuration phase */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
- puts("FPGA: Could not configure\n");
- return -2;
- }
-
- /* Clear all interrupts in CB Monitor */
- writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
-
- /* Enable AXI configuration */
- setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Write the RBF data to FPGA Manager */
-static void fpgamgr_program_write(const void *rbf_data, unsigned long rbf_size)
-{
- uint32_t src = (uint32_t)rbf_data;
- uint32_t dst = SOCFPGA_FPGAMGRDATA_ADDRESS;
-
- /* Number of loops for 32-byte long copying. */
- uint32_t loops32 = rbf_size / 32;
- /* Number of loops for 4-byte long copying + trailing bytes */
- uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
-
- asm volatile(
- "1: ldmia %0!, {r0-r7}\n"
- " stmia %1!, {r0-r7}\n"
- " sub %1, #32\n"
- " subs %2, #1\n"
- " bne 1b\n"
- " cmp %3, #0\n"
- " beq 3f\n"
- "2: ldr %2, [%0], #4\n"
- " str %2, [%1]\n"
- " subs %3, #1\n"
- " bne 2b\n"
- "3: nop\n"
- : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
- : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
-}
-
-/* Ensure the FPGA entering config done */
-static int fpgamgr_program_poll_cd(void)
-{
- const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
- FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
- unsigned long reg, i;
-
- /* (3) wait until full config done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- reg = readl(&fpgamgr_regs->gpio_ext_porta);
-
- /* Config error */
- if (!(reg & mask)) {
- printf("FPGA: Configuration error.\n");
- return -3;
- }
-
- /* Config done without error */
- if (reg & mask)
- break;
- }
-
- /* Timeout happened, return error */
- if (i == FPGA_TIMEOUT_CNT) {
- printf("FPGA: Timeout waiting for program.\n");
- return -4;
- }
-
- /* Disable AXI configuration */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
-
- return 0;
-}
-
-/* Ensure the FPGA entering init phase */
-static int fpgamgr_program_poll_initphase(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to enter initialization phase */
- if (fpgamgr_dclkcnt_set(0x4))
- return -5;
-
- /* (4) wait until FPGA enter init phase or user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
- break;
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
-
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -6;
-
- return 0;
-}
-
-/* Ensure the FPGA entering user mode */
-static int fpgamgr_program_poll_usermode(void)
-{
- unsigned long i;
-
- /* Additional clocks for the CB to exit initialization phase */
- if (fpgamgr_dclkcnt_set(0x5000))
- return -7;
-
- /* (5) wait until FPGA enter user mode */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
- break;
- }
- /* If not in configuration state, return error */
- if (i == FPGA_TIMEOUT_CNT)
- return -8;
-
- /* To release FPGA Manager drive over configuration line */
- clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
-
- return 0;
-}
-
-/*
- * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
- * Return 0 for sucess, non-zero for error.
- */
-int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
-{
- unsigned long status;
-
- if ((uint32_t)rbf_data & 0x3) {
- puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
- return -EINVAL;
- }
-
- /* Prior programming the FPGA, all bridges need to be shut off */
-
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- /* Disable all signals from hps peripheral controller to fpga */
- writel(0, &sysmgr_regs->fpgaintfgrp_module);
-#endif
-
- /* Disable all signals from FPGA to HPS SDRAM */
-#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
- writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
-
- /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
- socfpga_bridges_reset(1);
-
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
- /* Unmap the bridges from NIC-301 */
- writel(0x1, SOCFPGA_L3REGS_ADDRESS);
-#endif
-
- /* Initialize the FPGA Manager */
- status = fpgamgr_program_init();
- if (status)
- return status;
-
- /* Write the RBF data to FPGA Manager */
- fpgamgr_program_write(rbf_data, rbf_size);
-
- /* Ensure the FPGA entering config done */
- status = fpgamgr_program_poll_cd();
- if (status)
- return status;
-
- /* Ensure the FPGA entering init phase */
- status = fpgamgr_program_poll_initphase();
- if (status)
- return status;
-
- /* Ensure the FPGA entering user mode */
- return fpgamgr_program_poll_usermode();
-}
diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga_gen5.c
similarity index 91%
copy from drivers/fpga/socfpga.c
copy to drivers/fpga/socfpga_gen5.c
index 3751574..e553bd9 100644
--- a/drivers/fpga/socfpga.c
+++ b/drivers/fpga/socfpga_gen5.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -14,15 +14,10 @@
DECLARE_GLOBAL_DATA_PTR;
-/* Timeout count */
-#define FPGA_TIMEOUT_CNT 0x1000000
-
static struct socfpga_fpga_manager *fpgamgr_regs =
(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-#endif
/* Set CD ratio */
static void fpgamgr_set_cd_ratio(unsigned long ratio)
@@ -32,29 +27,6 @@ static void fpgamgr_set_cd_ratio(unsigned long ratio)
(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
}
-static int fpgamgr_dclkcnt_set(unsigned long cnt)
-{
- unsigned long i;
-
- /* Clear any existing done status */
- if (readl(&fpgamgr_regs->dclkstat))
- writel(0x1, &fpgamgr_regs->dclkstat);
-
- /* Write the dclkcnt */
- writel(cnt, &fpgamgr_regs->dclkcnt);
-
- /* Wait till the dclkcnt done */
- for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
- if (!readl(&fpgamgr_regs->dclkstat))
- continue;
-
- writel(0x1, &fpgamgr_regs->dclkstat);
- return 0;
- }
-
- return -ETIMEDOUT;
-}
-
/* Start the FPGA programming by initialize the FPGA Manager */
static int fpgamgr_program_init(void)
{
@@ -269,11 +241,8 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
}
/* Prior programming the FPGA, all bridges need to be shut off */
-
-#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Disable all signals from hps peripheral controller to fpga */
writel(0, &sysmgr_regs->fpgaintfgrp_module);
-#endif
/* Disable all signals from FPGA to HPS SDRAM */
#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
--
1.7.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver
2017-03-03 12:50 [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee Tien Fong
2017-03-03 12:50 ` [U-Boot] [PATCH 1/4] arm: socfpga: Removing unused passing parameter of socfpga_bridges_reset Chee Tien Fong
2017-03-03 12:50 ` [U-Boot] [PATCH 2/4] arm: socfpga: Restructure FPGA driver in the preparation to support A10 Chee Tien Fong
@ 2017-03-03 12:50 ` Chee Tien Fong
2017-03-03 12:50 ` [U-Boot] [PATCH 4/4] arm: socfpga: Add FPGA driver support for Arria 10 Chee Tien Fong
2017-03-06 4:38 ` [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
4 siblings, 0 replies; 11+ messages in thread
From: Chee Tien Fong @ 2017-03-03 12:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
This patch adding the Arria10 FPGA manager program assembly driver
which can be used for feeding bitstream to configure FPGA.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ching Liang See <chin.liang.see@intel.com>
Cc: Ley Foon <ley.foon.tan@intel.com>
Cc: Westergreen Dalon <dalon.westergreen@intel.com>
---
arch/arm/mach-socfpga/lowlevel_init.S | 48 +++++++++++++++++++++++++++++++++
1 files changed, 48 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
diff --git a/arch/arm/mach-socfpga/lowlevel_init.S b/arch/arm/mach-socfpga/lowlevel_init.S
new file mode 100644
index 0000000..79e9d07
--- /dev/null
+++ b/arch/arm/mach-socfpga/lowlevel_init.S
@@ -0,0 +1,48 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+
+/*
+ * Write RBF data in burst form to FPGA Manager
+ * [r0] RBF binary source address
+ * [r1] FPGA Manager data address
+ * [r2] RBF data length
+ */
+
+ENTRY(fpgamgr_axi_write)
+ PUSH {r4-r11, lr} /* save registers per AAPCS */
+
+write_burst:
+ cmp r2,#32
+ beq write_burst_cont
+ bls write_word
+write_burst_cont:
+ ldmia r0!, {r4-r11}
+ stmia r1, {r4-r11}
+ subs r2, r2, #32
+ b write_burst
+
+write_word:
+ cmp r2,#4
+ beq write_word_cont
+ bls write_byte
+write_word_cont:
+ ldmia r0!, {r4}
+ stmia r1, {r4}
+ subs r2, r2, #4
+ b write_word
+
+write_byte:
+ cmp r2,#0
+ beq write_end
+ ldr r3, [r0]
+ str r3, [r1]
+write_end:
+ POP {r4-r11, pc}
+ENDPROC(fpgamgr_axi_write)
--
1.7.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 4/4] arm: socfpga: Add FPGA driver support for Arria 10
2017-03-03 12:50 [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee Tien Fong
` (2 preceding siblings ...)
2017-03-03 12:50 ` [U-Boot] [PATCH 3/4] arm: socfpga: Add Arria10 FPGA manager program assembly driver Chee Tien Fong
@ 2017-03-03 12:50 ` Chee Tien Fong
2017-03-06 4:38 ` [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee, Tien Fong
4 siblings, 0 replies; 11+ messages in thread
From: Chee Tien Fong @ 2017-03-03 12:50 UTC (permalink / raw)
To: u-boot
From: Tien Fong Chee <tien.fong.chee@intel.com>
Add FPGA driver support for Arria 10.
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ching Liang See <chin.liang.see@intel.com>
Cc: Ley Foon <ley.foon.tan@intel.com>
Cc: Westergreen Dalon <dalon.westergreen@intel.com>
---
arch/arm/mach-socfpga/Makefile | 1 +
arch/arm/mach-socfpga/include/mach/fpga_manager.h | 2 +
.../include/mach/fpga_manager_arria10.h | 120 +++++
drivers/Makefile | 1 +
drivers/fpga/Makefile | 1 +
drivers/fpga/socfpga_arria10.c | 565 ++++++++++++++++++++
6 files changed, 690 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
create mode 100644 drivers/fpga/socfpga_arria10.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 901bf91..d1ca3ee 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -18,6 +18,7 @@ obj-y += clock_manager_arria10.o
obj-y += misc_arria10.o
obj-y += pinmux_arria10.o
obj-y += reset_manager_arria10.o
+obj-y += lowlevel_init.o
endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
index 76a9289..64e8344 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h
@@ -12,6 +12,8 @@
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
#endif
/* FPGA CD Ratio Value */
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
new file mode 100644
index 0000000..a273be7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FPGA_MANAGER_ARRIA10_H_
+#define _FPGA_MANAGER_ARRIA10_H_
+
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK 0x00000002
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 0x00000004
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK 0x00000010
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_OE_SET_MSK 0x00000020
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_READY_SET_MSK 0x00000200
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK 0x00000400
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK 0x00001000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK 0x00010000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK 0x00020000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK 0x00040000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD (\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK |\
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK)
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOFULL_SET_MSK 0x02000000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_JTAGM_SET_MSK 0x10000000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EMR_SET_MSK 0x20000000
+#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
+
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK 0x00000001
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK 0x00000002
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK 0x00000004
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK 0x00000100
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK 0x00010000
+#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK 0x01000000
+
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK 0x00000001
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK 0x00010000
+#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK 0x01000000
+
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK 0x00000001
+#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000
+#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
+
+/* Timeout counter */
+#define FPGA_TIMEOUT_CNT 0x1000000
+#define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
+
+#ifndef __ASSEMBLY__
+
+struct socfpga_fpga_manager {
+ uint32_t _pad_0x0_0x7[2];
+ uint32_t dclkcnt;
+ uint32_t dclkstat;
+ uint32_t gpo;
+ uint32_t gpi;
+ uint32_t misci;
+ uint32_t _pad_0x1c_0x2f[5];
+ uint32_t emr_data0;
+ uint32_t emr_data1;
+ uint32_t emr_data2;
+ uint32_t emr_data3;
+ uint32_t emr_data4;
+ uint32_t emr_data5;
+ uint32_t emr_valid;
+ uint32_t emr_en;
+ uint32_t jtag_config;
+ uint32_t jtag_status;
+ uint32_t jtag_kick;
+ uint32_t _pad_0x5c_0x5f;
+ uint32_t jtag_data_w;
+ uint32_t jtag_data_r;
+ uint32_t _pad_0x68_0x6f[2];
+ uint32_t imgcfg_ctrl_00;
+ uint32_t imgcfg_ctrl_01;
+ uint32_t imgcfg_ctrl_02;
+ uint32_t _pad_0x7c_0x7f;
+ uint32_t imgcfg_stat;
+ uint32_t intr_masked_status;
+ uint32_t intr_mask;
+ uint32_t intr_polarity;
+ uint32_t dma_config;
+ uint32_t imgcfg_fifo_status;
+};
+
+/* Functions */
+int is_fpgamgr_fpga_ready(void);
+int poll_fpgamgr_fpga_ready(void);
+int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size);
+int fpgamgr_program_fini(void);
+void fpgamgr_program_write(const unsigned long *rbf_data,
+ unsigned long rbf_size);
+void fpgamgr_program_sync(void);
+int fpgamgr_program_poll_cd(void);
+int fpgamgr_program_poll_initphase(void);
+int is_fpgamgr_user_mode(void);
+int fpgamgr_program_poll_usermode(void);
+int fpgamgr_program_poll_usermode(void);
+int fpgamgr_program_fpga(const unsigned long *rbf_data,
+ unsigned long rbf_size);
+void fpgamgr_axi_write(const unsigned long *rbf_data,
+ const unsigned long fpgamgr_data_addr, unsigned long rbf_size);
+int fpgamgr_wait_early_user_mode(void);
+int is_fpgamgr_early_user_mode(void);
+int fpgamgr_reset(void);
+int wait_for_nconfig_pin_and_nstatus_pin(void);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _FPGA_MANAGER_ARRIA10_H_ */
diff --git a/drivers/Makefile b/drivers/Makefile
index 6e7a2c3..375ee78 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM) += ram/
ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_FPGA) += fpga/
obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/
obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/
obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/
diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile
index c70ee40..bb063e0 100644
--- a/drivers/fpga/Makefile
+++ b/drivers/fpga/Makefile
@@ -22,5 +22,6 @@ obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
ifdef CONFIG_FPGA_SOCFPGA
obj-y += socfpga.o
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
endif
endif
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
new file mode 100644
index 0000000..e6c767b
--- /dev/null
+++ b/drivers/fpga/socfpga_arria10.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32 1
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+ (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+ (void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+ uint32_t reg;
+
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ reg = ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB);
+
+ return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+ if (width)
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+ else
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+/* Check whether FPGA Init_Done signal is high */
+int is_fpgamgr_initdone_high(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK) != 0;
+}
+
+int is_fpgamgr_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+ unsigned start = get_timer(0);
+
+ while (!(is_fpgamgr_user_mode())) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+int is_fpgamgr_early_user_mode(void)
+{
+ return (readl(&fpga_manager_base->imgcfg_stat) &
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+ u32 sync_data = 0xffffffff;
+ u32 i = 0;
+ unsigned start = get_timer(0);
+ unsigned long cd_ratio;
+
+ /* Getting existing CDRATIO */
+ cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+ /* Using CDRATIO_X1 for better compatibility */
+ fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+ while (!(is_fpgamgr_early_user_mode())) {
+ if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+ return -ETIMEDOUT;
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ udelay(1000);
+ i++;
+ }
+
+ debug("Additional %i sync word needed\n", i);
+
+ /* restoring original CDRATIO */
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+/* send sync words to clock data through the control block */
+void fpgamgr_program_sync(void)
+{
+ u32 sync_data = 0xffffffff;
+ int i;
+ for (i = 0; i < 10; i++) {
+ fpgamgr_program_write((const long unsigned int *)&sync_data,
+ sizeof(sync_data));
+ }
+}
+
+static int wait_for_imgcfg_stat(unsigned long mask)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & mask) == mask)
+ break;
+ }
+
+ return i;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+ return wait_for_imgcfg_stat(
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+ unsigned long reg, i, desired;
+ unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+ if (value == 0)
+ desired = 0;
+ else
+ desired = mask;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & mask) == desired)
+ break;
+ }
+
+ return i;
+}
+
+/* Check whether FPGA is ready to be accessed */
+int is_fpgamgr_fpga_ready(void)
+{
+ /* check for init done signal */
+ if (is_fpgamgr_initdone_high() == 0)
+ return 0;
+
+ /* check again to avoid false glitches */
+ if (is_fpgamgr_initdone_high() == 0)
+ return 0;
+
+ if (!is_fpgamgr_user_mode())
+ return 0;
+
+ return 1;
+}
+
+/* Poll until FPGA is ready to be accessed or timeout occurred */
+int poll_fpgamgr_fpga_ready(void)
+{
+ unsigned long i;
+
+ /* If FPGA is blank, wait till WD invoke warm reset */
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ /* check for init done signal */
+ if (is_fpgamgr_initdone_high() == 0)
+ continue;
+
+ /* check again to avoid false glitches */
+ if (is_fpgamgr_initdone_high() == 0)
+ continue;
+
+ return 1;
+ }
+
+ return 0;
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+ ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration mode */
+static int fpgamgr_verify_msel(void)
+{
+ unsigned int msel = fpgamgr_get_msel();
+
+ if ((msel != 0) && (msel != 1)) {
+ printf("Fail: read msel=%d\n", msel);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+ u32 rbf_size)
+{
+ unsigned int cd_ratio;
+ bool encrypt, compress;
+
+ if (rbf_size < 230)
+ return -1;
+
+ encrypt = (rbf_data[69] >> 2) & 3;
+ encrypt = encrypt != 0;
+
+ compress = (rbf_data[229] >> 1) & 1;
+ compress = !compress;
+
+#if 0
+ printf("header word %d = %08x\n", 69, rbf_data[69]);
+ printf("header word %d = %08x\n", 229, rbf_data[229]);
+ printf("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+#endif
+
+ /*
+ * from the register map description of cdratio in imgcfg_ctrl_02:
+ * Normal Configuration : 32bit Passive Parallel
+ * Partial Reconfiguration : 16bit Passive Parallel
+ */
+
+ /*
+ * cd ratio is dependent on cfg width and whether the bitstream
+ * is encrypted and/or compressed.
+ *
+ * | width | encr. | compr. | cd ratio |
+ * | 16 | 0 | 0 | 1 |
+ * | 16 | 0 | 1 | 4 |
+ * | 16 | 1 | 0 | 2 |
+ * | 16 | 1 | 1 | 4 |
+ * | 32 | 0 | 0 | 1 |
+ * | 32 | 0 | 1 | 8 |
+ * | 32 | 1 | 0 | 4 |
+ * | 32 | 1 | 1 | 8 |
+ */
+ if (!compress && !encrypt) {
+ cd_ratio = CDRATIO_x1;
+ } else {
+ if (compress)
+ cd_ratio = CDRATIO_x4;
+ else
+ cd_ratio = CDRATIO_x2;
+
+ /* if 32 bit, double the cd ratio (so register
+ field setting is incremented) */
+ if (cfg_width == CFGWDTH_32)
+ cd_ratio += 1;
+ }
+
+ fpgamgr_set_cfgwdth(cfg_width);
+ fpgamgr_set_cd_ratio(cd_ratio);
+
+ return 0;
+}
+
+int fpgamgr_reset(void)
+{
+ unsigned long reg;
+
+ /* S2F_NCONFIG = 0 */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 0 */
+ if (wait_for_f2s_nstatus_pin(0) == FPGA_TIMEOUT_CNT)
+ return -5;
+
+ /* S2F_NCONFIG = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ /* Wait for f2s_nstatus == 1 */
+ if (wait_for_f2s_nstatus_pin(1) == FPGA_TIMEOUT_CNT)
+ return -6;
+
+ /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
+ return -7;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
+ return -8;
+
+ return 0;
+}
+
+/* Start the FPGA programming by initialize the FPGA Manager */
+int fpgamgr_program_init(u32 * rbf_data, u32 rbf_size)
+{
+ int ret;
+
+ /* Step 1 */
+ if (fpgamgr_verify_msel())
+ return -1;
+
+ /* Step 2 */
+ if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
+ return -2;
+
+ /*
+ * Step 3:
+ * Make sure no other external devices are trying to interfere with
+ * programming:
+ */
+ if (wait_for_nconfig_pin_and_nstatus_pin() == FPGA_TIMEOUT_CNT)
+ return -3;
+
+ /*
+ * Step 4:
+ * Deassert the signal drives from HPS
+ *
+ * S2F_NCE = 1
+ * S2F_PR_REQUEST = 0
+ * EN_CFG_CTRL = 0
+ * EN_CFG_DATA = 0
+ * S2F_NCONFIG = 1
+ * S2F_NSTATUS_OE = 0
+ * S2F_CONDONE_OE = 0
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
+
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
+
+ /*
+ * Step 5:
+ * Enable overrides
+ * S2F_NENABLE_CONFIG = 0
+ * S2F_NENABLE_NCONFIG = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /*
+ * Disable driving signals that HPS doesn't need to drive.
+ * S2F_NENABLE_NSTATUS = 1
+ * S2F_NENABLE_CONDONE = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
+
+ /*
+ * Step 6:
+ * Drive chip select S2F_NCE = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /* Step 7 */
+ if (wait_for_nconfig_pin_and_nstatus_pin() == FPGA_TIMEOUT_CNT)
+ return -4;
+
+ /* Step 8 */
+ ret = fpgamgr_reset();
+ if (ret)
+ return ret;
+
+ /*
+ * Step 9:
+ * EN_CFG_CTRL and EN_CFG_DATA = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ return 0;
+}
+
+int fpgamgr_program_fini(void)
+{
+ /* Ensure the FPGA entering config done */
+ int status = fpgamgr_program_poll_cd();
+ if (status) {
+ printf("FPGA: Poll CD failed with error code %d\n", status);
+ return -3;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering init phase */
+ status = fpgamgr_program_poll_initphase();
+ if (status) {
+ printf("FPGA: Poll initphase failed with error code %d\n",
+ status);
+ return -4;
+ }
+ WATCHDOG_RESET();
+
+ /* Ensure the FPGA entering user mode */
+ status = fpgamgr_program_poll_usermode();
+ if (status) {
+ printf("FPGA: Poll usermode failed with error code %d\n",
+ status);
+ return -5;
+ }
+
+ printf("Full Configuration Succeeded.\n");
+
+ return 0;
+}
+
+/* Write the RBF data to FPGA Manager */
+void fpgamgr_program_write(const unsigned long *rbf_data,
+ unsigned long rbf_size)
+{
+ /* Write sof/pof data to img_data_w */
+ fpgamgr_axi_write(rbf_data, SOCFPGA_FPGAMGRDATA_ADDRESS, rbf_size);
+}
+
+/* Ensure the FPGA entering config done */
+int fpgamgr_program_poll_cd(void)
+{
+ unsigned long reg, i;
+
+ for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
+ return 0;
+
+ if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
+ printf("nstatus == 0 while waiting for condone\n");
+ return -9;
+ }
+ }
+
+ if (i == FPGA_TIMEOUT_CNT)
+ return -10;
+
+ return 0;
+}
+
+/* Ensure the FPGA entering init phase */
+int fpgamgr_program_poll_initphase(void)
+{
+ return 0;
+}
+
+/* Ensure the FPGA entering user mode */
+int fpgamgr_program_poll_usermode(void)
+{
+ unsigned long reg;
+ int ret = 0;
+
+ if (fpgamgr_dclkcnt_set(0xf) == FPGA_TIMEOUT_CNT)
+ return -11;
+
+ ret = wait_for_user_mode();
+
+ if (ret < 0) {
+ printf("%s: Failed to enter user mode with ", __func__);
+ printf("error code %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Step 14:
+ * Stop DATA path and Dclk
+ * EN_CFG_CTRL and EN_CFG_DATA = 0
+ */
+ clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
+ ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
+
+ /*
+ * Step 15:
+ * Disable overrides
+ * S2F_NENABLE_CONFIG = 1
+ * S2F_NENABLE_NCONFIG = 1
+ */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
+ ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
+
+ /* Disable chip select S2F_NCE = 1 */
+ setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
+ ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
+
+ /*
+ * Step 16:
+ * Final check
+ */
+ reg = readl(&fpga_manager_base->imgcfg_stat);
+ if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) == 0) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) == 0) ||
+ ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0))
+ return -13;
+
+ return 0;
+}
+
+/*
+ * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
+ * Return 0 for sucess, non-zero for error.
+ */
+int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+ unsigned long status;
+
+ /* disable all signals from hps peripheral controller to fpga */
+ writel(0, &system_manager_base->fpgaintf_en_global);
+
+ /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
+ socfpga_bridges_reset();
+
+ /* Initialize the FPGA Manager */
+ status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
+ if (status)
+ return status;
+
+ /* Write the RBF data to FPGA Manager */
+ fpgamgr_program_write(rbf_data, rbf_size);
+
+ return fpgamgr_program_fini();
+}
--
1.7.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver
2017-03-03 12:50 [U-Boot] [PATCH 0/4] Add Intel Arria 10 SoC FPGA driver Chee Tien Fong
` (3 preceding siblings ...)
2017-03-03 12:50 ` [U-Boot] [PATCH 4/4] arm: socfpga: Add FPGA driver support for Arria 10 Chee Tien Fong
@ 2017-03-06 4:38 ` Chee, Tien Fong
4 siblings, 0 replies; 11+ messages in thread
From: Chee, Tien Fong @ 2017-03-06 4:38 UTC (permalink / raw)
To: u-boot
On Jum, 2017-03-03 at 20:50 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This patchset adds FPGA driver to Intel Arria 10 SoC.
>
> This series is working on top of [1] initial patchset which enables
> the basic
> support for Arria 10 and other features.
>
> [1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg240053.html
>
> Regards,
> Tien Fong
>
> Tien Fong Chee (4):
> arm: socfpga: Removing unused passing parameter of
> socfpga_bridges_reset
> arm: socfpga: Restructure FPGA driver in the preparation to support
> A10.
> arm: socfpga: Add Arria10 FPGA manager program assembly driver
> arm: socfpga: Add FPGA driver support for Arria 10
>
> arch/arm/mach-socfpga/Makefile | 3 +-
> arch/arm/mach-socfpga/include/mach/fpga_manager.h | 70 +--
> .../include/mach/fpga_manager_arria10.h | 120 +++++
> .../mach/{fpga_manager.h => fpga_manager_gen5.h} | 66 ++--
> arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 -
> .../include/mach/reset_manager_arria10.h | 1 +
> .../mach-socfpga/include/mach/reset_manager_gen5.h | 1 +
> arch/arm/mach-socfpga/lowlevel_init.S | 48 ++
> arch/arm/mach-socfpga/reset_manager_arria10.c | 2 +-
> drivers/Makefile | 1 +
> drivers/fpga/Makefile | 6 +-
> drivers/fpga/socfpga.c | 272 +---------
> -
> drivers/fpga/socfpga_arria10.c | 565
> ++++++++++++++++++++
> drivers/fpga/{socfpga.c => socfpga_gen5.c} | 33 +--
> 14 files changed, 792 insertions(+), 399 deletions(-)
> create mode 100644 arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h =>
> fpga_manager_gen5.h} (85%)
> mode change 100755 => 100644 arch/arm/mach-
> socfpga/include/mach/reset_manager_arria10.h
> mode change 100755 => 100644 arch/arm/mach-
> socfpga/include/mach/reset_manager_gen5.h
> create mode 100644 arch/arm/mach-socfpga/lowlevel_init.S
> create mode 100644 drivers/fpga/socfpga_arria10.c
> copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (91%)
>
+CC Marek, Dinh, LF, Dalon, CL ...
This is cover letter for this series patches https://www.mail-archive.c
om/u-boot at lists.denx.de/msg240843.html
^ permalink raw reply [flat|nested] 11+ messages in thread