[U-Boot] [PATCH 4/4] mx25pdk: Set the eSDHC PER clock to 48 MHz

Fabio Estevam
2017-05-29T11:20:01Z

On Wed, May 3, 2017 at 6:59 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote:
> The maximum SD clock frequency in High Speed mode is 50 MHz. This change
> makes it possible to get 48 MHz from the USB PLL (240 MHz / 5 / 1)
> instead of the previous 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>
> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>