[U-Boot] [PATCH 1/4] mmc: fsl_esdhc: Allow all supported prescaler values

Fabio Estevam
2017-05-29T11:17:34Z

On Wed, May 3, 2017 at 6:59 AM, Benoît Thébaudeau <benoit@wsystem.com> wrote:
> On i.MX, SYSCTL.SDCLKFS may be set to 0 in order to make the SD clock
> frequency prescaler divide by 1 in SDR mode. In DDR mode, the prescaler
> can divide by up to 512. Allow both of these settings.
>
> The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
> this change makes it possible to get 48 MHz from the USB PLL
> (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
> (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>
> Signed-off-by: Benoît Thébaudeau <benoit@wsystem.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>