[U-Boot] [PATCH v3 5/6] MIPS: add support for Broadcom MIPS BCM6348 SoC family

Álvaro Fernández Rojas
2017-05-16T16:39:03Z

Reviewed-by: Simon Glass <sjg@chromium.org>
---
arch/mips/dts/brcm,bcm6348.dtsi | 127 ++++++++++++++++++++++++++++++
arch/mips/mach-bmips/Kconfig | 12 +++
arch/mips/mach-bmips/include/ioremap.h | 3 +-
include/configs/bmips_bcm6348.h | 30 +++++++
include/dt-bindings/clock/bcm6348-clock.h | 22 ++++++
include/dt-bindings/reset/bcm6348-reset.h | 22 ++++++
6 files changed, 215 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/dts/brcm,bcm6348.dtsi
create mode 100644 include/configs/bmips_bcm6348.h
create mode 100644 include/dt-bindings/clock/bcm6348-clock.h
create mode 100644 include/dt-bindings/reset/bcm6348-reset.h

diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi
new file mode 100644
index 0000000..711b643
--- /dev/null
+++ b/arch/mips/dts/brcm,bcm6348.dtsi
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6348-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6348-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "brcm,bcm6348";
+
+ cpus {
+ reg = <0xfffe0000 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ u-boot,dm-pre-reloc;
+
+ cpu at 0 {
+ compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
+ device_type = "cpu";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ periph_osc: periph-osc {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ u-boot,dm-pre-reloc;
+ };
+
+ periph_clk: periph-clk {
+ compatible = "brcm,bcm6345-clk";
+ reg = <0xfffe0004 0x4>;
+ #clock-cells = <1>;
+ };
+ };
+
+ pflash: nor at 1fc00000 {
+ compatible = "cfi-flash";
+ reg = <0x1fc00000 0x2000000>;
+ bank-width = <2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ status = "disabled";
+ };
+
+ ubus {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ u-boot,dm-pre-reloc;
+
+ pll_cntl: syscon at fffe0008 {
+ compatible = "syscon";
+ reg = <0xfffe0008 0x4>;
+ };
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ regmap = <&pll_cntl>;
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+
+ periph_rst: reset-controller at fffe0028 {
+ compatible = "brcm,bcm6345-reset";
+ reg = <0xfffe0028 0x4>;
+ #reset-cells = <1>;
+ };
+
+ wdt: watchdog at fffe021c {
+ compatible = "brcm,bcm6345-wdt";
+ reg = <0xfffe021c 0xc>;
+ clocks = <&periph_osc>;
+ };
+
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <&wdt>;
+ };
+
+ uart0: serial at fffe0300 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0xfffe0300 0x18>;
+ clocks = <&periph_osc>;
+
+ status = "disabled";
+ };
+
+ gpio1: gpio-controller at fffe0400 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <5>;
+
+ status = "disabled";
+ };
+
+ gpio0: gpio-controller at fffe0404 {
+ compatible = "brcm,bcm6345-gpio";
+ reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ status = "disabled";
+ };
+
+ memory-controller at fffe2300 {
+ compatible = "brcm,bcm6338-mc";
+ reg = <0xfffe2300 0x38>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 4a0c383..b7f7b1e 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -3,6 +3,7 @@ menu "Broadcom MIPS platforms"

config SYS_SOC
default "bcm6328" if SOC_BMIPS_BCM6328
+ default "bcm6348" if SOC_BMIPS_BCM6348
default "bcm6358" if SOC_BMIPS_BCM6358
default "bcm63268" if SOC_BMIPS_BCM63268

@@ -20,6 +21,17 @@ config SOC_BMIPS_BCM6328
help
This supports BMIPS BCM6328 family including BCM63281 and BCM63283.

+config SOC_BMIPS_BCM6348
+ bool "BMIPS BCM6348 family"
+ select SUPPORTS_BIG_ENDIAN
+ select SUPPORTS_CPU_MIPS32_R1
+ select MIPS_TUNE_4KC
+ select MIPS_L1_CACHE_SHIFT_4
+ select SWAP_IO_SPACE
+ select SYSRESET_WATCHDOG
+ help
+ This supports BMIPS BCM6348 family.
+
config SOC_BMIPS_BCM6358
bool "BMIPS BCM6358 family"
select SUPPORTS_BIG_ENDIAN
diff --git a/arch/mips/mach-bmips/include/ioremap.h b/arch/mips/mach-bmips/include/ioremap.h
index 404690e..d3dc0b8 100644
--- a/arch/mips/mach-bmips/include/ioremap.h
+++ b/arch/mips/mach-bmips/include/ioremap.h
@@ -18,7 +18,8 @@ static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr,

static inline int is_bmips_internal_registers(phys_addr_t offset)
{
-#if defined(CONFIG_SOC_BMIPS_BCM6358)
+#if defined(CONFIG_SOC_BMIPS_BCM6348) || \
+ defined(CONFIG_SOC_BMIPS_BCM6358)
if (offset >= 0xfffe0000)
return 1;
#endif
diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h
new file mode 100644
index 0000000..e9f53d6
--- /dev/null
+++ b/include/configs/bmips_bcm6348.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6348_H
+#define __CONFIG_BMIPS_BCM6348_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xbfc00000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
+
+#endif /* __CONFIG_BMIPS_BCM6348_H */
diff --git a/include/dt-bindings/clock/bcm6348-clock.h b/include/dt-bindings/clock/bcm6348-clock.h
new file mode 100644
index 0000000..5af066b
--- /dev/null
+++ b/include/dt-bindings/clock/bcm6348-clock.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6348_H
+#define __DT_BINDINGS_CLOCK_BCM6348_H
+
+#define BCM6348_CLK_ADSL 0
+#define BCM6348_CLK_MPI 1
+#define BCM6348_CLK_SDRAM 2
+#define BCM6348_CLK_M2M 3
+#define BCM6348_CLK_ENET 4
+#define BCM6348_CLK_SAR 5
+#define BCM6348_CLK_USBS 6
+#define BCM6348_CLK_USBH 8
+#define BCM6348_CLK_SPI 9
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6348_H */
diff --git a/include/dt-bindings/reset/bcm6348-reset.h b/include/dt-bindings/reset/bcm6348-reset.h
new file mode 100644
index 0000000..173937b
--- /dev/null
+++ b/include/dt-bindings/reset/bcm6348-reset.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6348_H
+#define __DT_BINDINGS_RESET_BCM6348_H
+
+#define BCM6348_RST_SPI 0
+#define BCM6348_RST_ENET 2
+#define BCM6348_RST_USBH 3
+#define BCM6348_RST_USBS 4
+#define BCM6348_RST_ADSL 5
+#define BCM6348_RST_DMAMEM 6
+#define BCM6348_RST_SAR 7
+#define BCM6348_RST_ACLC 8
+#define BCM6348_RST_ADSL_MIPS 10
+
+#endif /* __DT_BINDINGS_RESET_BCM6348_H */
--
2.1.4