From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Mon, 5 Jun 2017 12:11:25 +0000 Subject: [U-Boot] [PATCH v7 3/6] arm: socfpga: Enable FPGA driver on SPL In-Reply-To: <1e3479e8-af32-0ebe-0b94-dffdc3f6cb51@denx.de> References: <1496030410-8263-1-git-send-email-tien.fong.chee@intel.com> <1496030410-8263-4-git-send-email-tien.fong.chee@intel.com> <1496633548.2428.5.camel@intel.com> <1496635319.2428.14.camel@intel.com> <0458bef5-e220-4296-961f-ce1919101796@denx.de> <1496664396.2428.24.camel@intel.com> <1e3479e8-af32-0ebe-0b94-dffdc3f6cb51@denx.de> Message-ID: <1496664685.2428.25.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Isn, 2017-06-05 at 14:08 +0200, Marek Vasut wrote: > On 06/05/2017 02:06 PM, Chee, Tien Fong wrote: > > > > On Isn, 2017-06-05 at 13:24 +0200, Marek Vasut wrote: > > > > > > On 06/05/2017 06:02 AM, Chee, Tien Fong wrote: > > > > > > > > > > > > On Isn, 2017-06-05 at 11:32 +0800, Chee, Tien Fong wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > On Sab, 2017-06-03 at 13:27 +0200, Marek Vasut wrote: > > > > > > > > > > > > > > > > > > > > > > > > On 05/29/2017 06:00 AM, tien.fong.chee at intel.com wrote: > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > > From: Tien Fong Chee > > > > > > > > > > > > > > This patch is for enabling the FPGA driver support on > > > > > > > SPL. > > > > > > > > > > > > > > Signed-off-by: Tien Fong Chee > > > > > > > --- > > > > > > >  include/configs/socfpga_common.h | 1 + > > > > > > >  1 file changed, 1 insertion(+) > > > > > > > > > > > > > > diff --git a/include/configs/socfpga_common.h > > > > > > > b/include/configs/socfpga_common.h > > > > > > > index da7e4ad..e74e7eb 100644 > > > > > > > --- a/include/configs/socfpga_common.h > > > > > > > +++ b/include/configs/socfpga_common.h > > > > > > > @@ -110,6 +110,7 @@ > > > > > > >  #define CONFIG_FPGA > > > > > > >  #define CONFIG_FPGA_ALTERA > > > > > > >  #define CONFIG_FPGA_SOCFPGA > > > > > > > +#define CONFIG_SPL_FPGA_SUPPORT > > > > > > This should be Kconfig symbol selected in board config. Why > > > > > > is > > > > > > it > > > > > > not > > > > > > Kconfig symbol ? > > > > > > > > > > Ahha....ijust recalled there is a very important reason i did > > > > this > > > > because CONFIG_CMD_FPGA which is wrapping all these FPGA > > > > related > > > > CONFIG > > > > is not part of kconfig. > > > it is, so this is nonsense, try git grep next time ... > > > cmd/Kconfig:config CMD_FPGA > > > > > > > > > > > > > > > During the build, kconfig and Macro #define are > > > > in two different phase/order, so we might having build issue > > > > during > > > > kconfig build(1st phase) when some Macro #define which is 2nd > > > > phase > > > > are > > > > required. > > > I don't understand this, but I think this is bogus. > > > > > Okay. For example, CONFIG_A in Kconfig depend on CONFIG_B which is > > defined in socfpga_common.h. When SPL build, CONFIG_A would not be > > set > > to one even CONFIG_B is defined to one in header file, because at > > that > > moment build, CONFIG_B is not detected, but header file only get > > build > > after Kconfig build done. > Then convert whatever is missing to Kconfig and it's done ? > Yeah, i will send out immediately after this patch set.