[U-Boot] [PATCH 0/7] serial: mxc: Add debug uart support

[U-Boot] [PATCH 0/7] serial: mxc: Add debug uart support

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

This set add debug uart support by cleaning up exising 
serial_mxc

Jagan Teki (7):
  serial: mxc: Add common mxc_uart reg space
  serial: mxc: Use RFDIV in dm-code
  serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg
  serial: mxc: Move common init into _mxc_serial_init
  serial: mxc: Move common baud gen into _mxc_serial_setbrg
  serial: mxc: Code cleanup
  serial: mxc: Add debug uart support

 configs/imx6qdl_icore_mmc_defconfig |   4 +
 drivers/serial/Kconfig              |   8 +
 drivers/serial/serial_mxc.c         | 387 ++++++++++++++++++------------------
 3 files changed, 205 insertions(+), 194 deletions(-)

-- 
1.9.1

[U-Boot] [PATCH 1/7] serial: mxc: Add common mxc_uart reg space

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

This patch will add common reg space for non-dm and
dm code and non-dm reg space can be accessed using
mxc_base.

This will
- get rid of __REG volatile assignments
- Make common reg_space by removing unneeded macros

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 115 +++++++++++++++++++-------------------------
 1 file changed, 49 insertions(+), 66 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 64126e2..6d1d447 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -110,32 +110,39 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+struct mxc_uart {
+	u32 rxd;
+	u32 spare0[15];
+
+	u32 txd;
+	u32 spare1[15];
+
+	u32 cr1;
+	u32 cr2;
+	u32 cr3;
+	u32 cr4;
+
+	u32 fcr;
+	u32 sr1;
+	u32 sr2;
+	u32 esc;
+
+	u32 tim;
+	u32 bir;
+	u32 bmr;
+	u32 brc;
+
+	u32 onems;
+	u32 ts;
+};
+
 #ifndef CONFIG_DM_SERIAL
 
 #ifndef CONFIG_MXC_UART_BASE
 #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
 #endif
 
-#define UART_PHYS	CONFIG_MXC_UART_BASE
-
-#define __REG(x)     (*((volatile u32 *)(x)))
-
-/* Register definitions */
-#define URXD  0x0  /* Receiver Register */
-#define UTXD  0x40 /* Transmitter Register */
-#define UCR1  0x80 /* Control Register 1 */
-#define UCR2  0x84 /* Control Register 2 */
-#define UCR3  0x88 /* Control Register 3 */
-#define UCR4  0x8c /* Control Register 4 */
-#define UFCR  0x90 /* FIFO Control Register */
-#define USR1  0x94 /* Status Register 1 */
-#define USR2  0x98 /* Status Register 2 */
-#define UESC  0x9c /* Escape Character Register */
-#define UTIM  0xa0 /* Escape Timer Register */
-#define UBIR  0xa4 /* BRM Incremental Register */
-#define UBMR  0xa8 /* BRM Modulator Register */
-#define UBRC  0xac /* Baud Rate Count Register */
-#define UTS   0xb4 /* UART Test Register (mx31) */
+#define mxc_base	((struct mxc_uart *)CONFIG_MXC_UART_BASE)
 
 #define TXTL  2 /* reset default */
 #define RXTL  1 /* reset default */
@@ -148,19 +155,20 @@ static void mxc_serial_setbrg(void)
 	if (!gd->baudrate)
 		gd->baudrate = CONFIG_BAUDRATE;
 
-	__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
-		| (TXTL << UFCR_TXTL_SHF)
-		| (RXTL << UFCR_RXTL_SHF);
-	__REG(UART_PHYS + UBIR) = 0xf;
-	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
+	writel(((RFDIV << UFCR_RFDIV_SHF) |
+		(TXTL << UFCR_TXTL_SHF) |
+		(RXTL << UFCR_RXTL_SHF)),
+		&mxc_base->fcr);
+	writel(0xf, &mxc_base->bir);
+	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
 
 }
 
 static int mxc_serial_getc(void)
 {
-	while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
 		WATCHDOG_RESET();
-	return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
+	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
 }
 
 static void mxc_serial_putc(const char c)
@@ -169,10 +177,10 @@ static void mxc_serial_putc(const char c)
 	if (c == '\n')
 		serial_putc('\r');
 
-	__REG(UART_PHYS + UTXD) = c;
+	writel(c, &mxc_base->txd);
 
 	/* wait for transmitter to be ready */
-	while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
+	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
 		WATCHDOG_RESET();
 }
 
@@ -182,7 +190,7 @@ static void mxc_serial_putc(const char c)
 static int mxc_serial_tstc(void)
 {
 	/* If receive fifo is empty, return false */
-	if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
+	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
 		return 0;
 	return 1;
 }
@@ -194,23 +202,24 @@ static int mxc_serial_tstc(void)
  */
 static int mxc_serial_init(void)
 {
-	__REG(UART_PHYS + UCR1) = 0x0;
-	__REG(UART_PHYS + UCR2) = 0x0;
+	writel(0, &mxc_base->cr1);
+	writel(0, &mxc_base->cr2);
 
-	while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
+	while (!(readl(&mxc_base->cr2) & UCR2_SRST));
 
-	__REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
-	__REG(UART_PHYS + UCR4) = 0x8000;
-	__REG(UART_PHYS + UESC) = 0x002b;
-	__REG(UART_PHYS + UTIM) = 0x0;
+	writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3);
+	writel(0x8000, &mxc_base->cr4);
+	writel(0x2b, &mxc_base->esc);
+	writel(0, &mxc_base->tim);
 
-	__REG(UART_PHYS + UTS) = 0x0;
+	writel(0, &mxc_base->ts);
 
 	serial_setbrg();
 
-	__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
+	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+	       &mxc_base->cr2);
 
-	__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
+	writel(UCR1_UARTEN, &mxc_base->cr1);
 
 	return 0;
 }
@@ -239,32 +248,6 @@ __weak struct serial_device *default_serial_console(void)
 
 #ifdef CONFIG_DM_SERIAL
 
-struct mxc_uart {
-	u32 rxd;
-	u32 spare0[15];
-
-	u32 txd;
-	u32 spare1[15];
-
-	u32 cr1;
-	u32 cr2;
-	u32 cr3;
-	u32 cr4;
-
-	u32 fcr;
-	u32 sr1;
-	u32 sr2;
-	u32 esc;
-
-	u32 tim;
-	u32 bir;
-	u32 bmr;
-	u32 brc;
-
-	u32 onems;
-	u32 ts;
-};
-
 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct mxc_serial_platdata *plat = dev->platdata;
-- 
1.9.1

[U-Boot] [PATCH 1/7] serial: mxc: Add common mxc_uart reg space

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> This patch will add common reg space for non-dm and
> dm code and non-dm reg space can be accessed using
> mxc_base.
>
> This will
> - get rid of __REG volatile assignments
> - Make common reg_space by removing unneeded macros
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 115 +++++++++++++++++++-------------------------
>  1 file changed, 49 insertions(+), 66 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 1/7] serial: mxc: Add common mxc_uart reg space

[Stefano Babic]

On 06/06/2017 07:31, Jagan Teki wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
> 
> This patch will add common reg space for non-dm and
> dm code and non-dm reg space can be accessed using
> mxc_base.
> 
> This will
> - get rid of __REG volatile assignments
> - Make common reg_space by removing unneeded macros
> 
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 115 +++++++++++++++++++-------------------------
>  1 file changed, 49 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
> index 64126e2..6d1d447 100644
> --- a/drivers/serial/serial_mxc.c
> +++ b/drivers/serial/serial_mxc.c
> @@ -110,32 +110,39 @@
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +struct mxc_uart {
> +	u32 rxd;
> +	u32 spare0[15];
> +
> +	u32 txd;
> +	u32 spare1[15];
> +
> +	u32 cr1;
> +	u32 cr2;
> +	u32 cr3;
> +	u32 cr4;
> +
> +	u32 fcr;
> +	u32 sr1;
> +	u32 sr2;
> +	u32 esc;
> +
> +	u32 tim;
> +	u32 bir;
> +	u32 bmr;
> +	u32 brc;
> +
> +	u32 onems;
> +	u32 ts;
> +};
> +
>  #ifndef CONFIG_DM_SERIAL
>  
>  #ifndef CONFIG_MXC_UART_BASE
>  #error "define CONFIG_MXC_UART_BASE to use the MXC UART driver"
>  #endif
>  
> -#define UART_PHYS	CONFIG_MXC_UART_BASE
> -
> -#define __REG(x)     (*((volatile u32 *)(x)))
> -
> -/* Register definitions */
> -#define URXD  0x0  /* Receiver Register */
> -#define UTXD  0x40 /* Transmitter Register */
> -#define UCR1  0x80 /* Control Register 1 */
> -#define UCR2  0x84 /* Control Register 2 */
> -#define UCR3  0x88 /* Control Register 3 */
> -#define UCR4  0x8c /* Control Register 4 */
> -#define UFCR  0x90 /* FIFO Control Register */
> -#define USR1  0x94 /* Status Register 1 */
> -#define USR2  0x98 /* Status Register 2 */
> -#define UESC  0x9c /* Escape Character Register */
> -#define UTIM  0xa0 /* Escape Timer Register */
> -#define UBIR  0xa4 /* BRM Incremental Register */
> -#define UBMR  0xa8 /* BRM Modulator Register */
> -#define UBRC  0xac /* Baud Rate Count Register */
> -#define UTS   0xb4 /* UART Test Register (mx31) */
> +#define mxc_base	((struct mxc_uart *)CONFIG_MXC_UART_BASE)
>  
>  #define TXTL  2 /* reset default */
>  #define RXTL  1 /* reset default */
> @@ -148,19 +155,20 @@ static void mxc_serial_setbrg(void)
>  	if (!gd->baudrate)
>  		gd->baudrate = CONFIG_BAUDRATE;
>  
> -	__REG(UART_PHYS + UFCR) = (RFDIV << UFCR_RFDIV_SHF)
> -		| (TXTL << UFCR_TXTL_SHF)
> -		| (RXTL << UFCR_RXTL_SHF);
> -	__REG(UART_PHYS + UBIR) = 0xf;
> -	__REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate);
> +	writel(((RFDIV << UFCR_RFDIV_SHF) |
> +		(TXTL << UFCR_TXTL_SHF) |
> +		(RXTL << UFCR_RXTL_SHF)),
> +		&mxc_base->fcr);
> +	writel(0xf, &mxc_base->bir);
> +	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
>  
>  }
>  
>  static int mxc_serial_getc(void)
>  {
> -	while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
> +	while (readl(&mxc_base->ts) & UTS_RXEMPTY)
>  		WATCHDOG_RESET();
> -	return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
> +	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
>  }
>  
>  static void mxc_serial_putc(const char c)
> @@ -169,10 +177,10 @@ static void mxc_serial_putc(const char c)
>  	if (c == '\n')
>  		serial_putc('\r');
>  
> -	__REG(UART_PHYS + UTXD) = c;
> +	writel(c, &mxc_base->txd);
>  
>  	/* wait for transmitter to be ready */
> -	while (!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY))
> +	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
>  		WATCHDOG_RESET();
>  }
>  
> @@ -182,7 +190,7 @@ static void mxc_serial_putc(const char c)
>  static int mxc_serial_tstc(void)
>  {
>  	/* If receive fifo is empty, return false */
> -	if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
> +	if (readl(&mxc_base->ts) & UTS_RXEMPTY)
>  		return 0;
>  	return 1;
>  }
> @@ -194,23 +202,24 @@ static int mxc_serial_tstc(void)
>   */
>  static int mxc_serial_init(void)
>  {
> -	__REG(UART_PHYS + UCR1) = 0x0;
> -	__REG(UART_PHYS + UCR2) = 0x0;
> +	writel(0, &mxc_base->cr1);
> +	writel(0, &mxc_base->cr2);
>  
> -	while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
> +	while (!(readl(&mxc_base->cr2) & UCR2_SRST));
>  
> -	__REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
> -	__REG(UART_PHYS + UCR4) = 0x8000;
> -	__REG(UART_PHYS + UESC) = 0x002b;
> -	__REG(UART_PHYS + UTIM) = 0x0;
> +	writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3);
> +	writel(0x8000, &mxc_base->cr4);
> +	writel(0x2b, &mxc_base->esc);
> +	writel(0, &mxc_base->tim);
>  
> -	__REG(UART_PHYS + UTS) = 0x0;
> +	writel(0, &mxc_base->ts);
>  
>  	serial_setbrg();
>  
> -	__REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST;
> +	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
> +	       &mxc_base->cr2);
>  
> -	__REG(UART_PHYS + UCR1) = UCR1_UARTEN;
> +	writel(UCR1_UARTEN, &mxc_base->cr1);
>  
>  	return 0;
>  }
> @@ -239,32 +248,6 @@ __weak struct serial_device *default_serial_console(void)
>  
>  #ifdef CONFIG_DM_SERIAL
>  
> -struct mxc_uart {
> -	u32 rxd;
> -	u32 spare0[15];
> -
> -	u32 txd;
> -	u32 spare1[15];
> -
> -	u32 cr1;
> -	u32 cr2;
> -	u32 cr3;
> -	u32 cr4;
> -
> -	u32 fcr;
> -	u32 sr1;
> -	u32 sr2;
> -	u32 esc;
> -
> -	u32 tim;
> -	u32 bir;
> -	u32 bmr;
> -	u32 brc;
> -
> -	u32 onems;
> -	u32 ts;
> -};
> -
>  int mxc_serial_setbrg(struct udevice *dev, int baudrate)
>  {
>  	struct mxc_serial_platdata *plat = dev->platdata;
> 

Applied (whole series) to u-boot-imx, -next, thanks !

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic at denx.de
=====================================================================

[U-Boot] [PATCH 2/7] serial: mxc: Use RFDIV in dm-code

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Use RFDIV in dm-code instead of numeric value, so-that
it can be common for dm and non-dm.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 6d1d447..65c301d 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -76,6 +76,7 @@
 #define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 #define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 #define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
+#define RFDIV		4 /* divide input clock by 2 */
 #define  UFCR_DCEDTE	 (1<<6)  /* DTE mode select */
 #define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 #define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
@@ -106,7 +107,7 @@
 #define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
 #define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
 #define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
-#define  UTS_SOFTRST	 (1<<0)	 /* Software reset */
+#define  UTS_SOFTRS	(1<<0)	 /* Software reset */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -146,7 +147,6 @@ struct mxc_uart {
 
 #define TXTL  2 /* reset default */
 #define RXTL  1 /* reset default */
-#define RFDIV 4 /* divide input clock by 2 */
 
 static void mxc_serial_setbrg(void)
 {
@@ -255,7 +255,7 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 	u32 clk = imx_get_uartclk();
 	u32 tmp;
 
-	tmp = 4 << UFCR_RFDIV_SHF;
+	tmp = RFDIV << UFCR_RFDIV_SHF;
 	if (plat->use_dte)
 		tmp |= UFCR_DCEDTE;
 	writel(tmp, &uart->fcr);
-- 
1.9.1

[U-Boot] [PATCH 2/7] serial: mxc: Use RFDIV in dm-code

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Use RFDIV in dm-code instead of numeric value, so-that
> it can be common for dm and non-dm.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 3/7] serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Control reg write should be part of setbrg for better
buadrate generation, so move cr1 and cr2 write to
mxc_serial_setbrg

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 65c301d..288b610 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -162,6 +162,9 @@ static void mxc_serial_setbrg(void)
 	writel(0xf, &mxc_base->bir);
 	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
 
+	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+	       &mxc_base->cr2);
+	writel(UCR1_UARTEN, &mxc_base->cr1);
 }
 
 static int mxc_serial_getc(void)
@@ -216,11 +219,6 @@ static int mxc_serial_init(void)
 
 	serial_setbrg();
 
-	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
-	       &mxc_base->cr2);
-
-	writel(UCR1_UARTEN, &mxc_base->cr1);
-
 	return 0;
 }
 
-- 
1.9.1

[U-Boot] [PATCH 3/7] serial: mxc: Move cr1 and cr2 write to mxc_serial_setbrg

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Control reg write should be part of setbrg for better
> buadrate generation, so move cr1 and cr2 write to
> mxc_serial_setbrg
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 8 +++-----
>  1 file changed, 3 insertions(+), 5 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 4/7] serial: mxc: Move common init into _mxc_serial_init

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Move the common initialization code into _mxc_serial_init
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 37 +++++++++++++++++--------------------
 1 file changed, 17 insertions(+), 20 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 288b610..4b19052 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -137,6 +137,21 @@ struct mxc_uart {
 	u32 ts;
 };
 
+static void _mxc_serial_init(struct mxc_uart *base)
+{
+	writel(0, &base->cr1);
+	writel(0, &base->cr2);
+
+	while (!(readl(&base->cr2) & UCR2_SRST));
+
+	writel(0x704 | UCR3_ADNIMP, &base->cr3);
+	writel(0x8000, &base->cr4);
+	writel(0x2b, &base->esc);
+	writel(0, &base->tim);
+
+	writel(0, &base->ts);
+}
+
 #ifndef CONFIG_DM_SERIAL
 
 #ifndef CONFIG_MXC_UART_BASE
@@ -205,17 +220,7 @@ static int mxc_serial_tstc(void)
  */
 static int mxc_serial_init(void)
 {
-	writel(0, &mxc_base->cr1);
-	writel(0, &mxc_base->cr2);
-
-	while (!(readl(&mxc_base->cr2) & UCR2_SRST));
-
-	writel(0x704 | UCR3_ADNIMP, &mxc_base->cr3);
-	writel(0x8000, &mxc_base->cr4);
-	writel(0x2b, &mxc_base->esc);
-	writel(0, &mxc_base->tim);
-
-	writel(0, &mxc_base->ts);
+	_mxc_serial_init(mxc_base);
 
 	serial_setbrg();
 
@@ -271,16 +276,8 @@ int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 static int mxc_serial_probe(struct udevice *dev)
 {
 	struct mxc_serial_platdata *plat = dev->platdata;
-	struct mxc_uart *const uart = plat->reg;
 
-	writel(0, &uart->cr1);
-	writel(0, &uart->cr2);
-	while (!(readl(&uart->cr2) & UCR2_SRST));
-	writel(0x704 | UCR3_ADNIMP, &uart->cr3);
-	writel(0x8000, &uart->cr4);
-	writel(0x2b, &uart->esc);
-	writel(0, &uart->tim);
-	writel(0, &uart->ts);
+	_mxc_serial_init(plat->reg);
 
 	return 0;
 }
-- 
1.9.1

[U-Boot] [PATCH 4/7] serial: mxc: Move common init into _mxc_serial_init

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Move the common initialization code into _mxc_serial_init
> so-that dm and non-dm can call this func.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 37 +++++++++++++++++--------------------
>  1 file changed, 17 insertions(+), 20 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 5/7] serial: mxc: Move common baud gen into _mxc_serial_setbrg

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Move the common baud generation code into _mxc_serial_setbrg
so-that dm and non-dm can call this func.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 50 ++++++++++++++++++++++-----------------------
 1 file changed, 24 insertions(+), 26 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 4b19052..0fd3aaa 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -108,6 +108,8 @@
 #define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
 #define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
 #define  UTS_SOFTRS	(1<<0)	 /* Software reset */
+#define TXTL		2  /* reset default */
+#define RXTL		1  /* reset default */
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -152,6 +154,26 @@ static void _mxc_serial_init(struct mxc_uart *base)
 	writel(0, &base->ts);
 }
 
+static void _mxc_serial_setbrg(struct mxc_uart *base, unsigned long clk,
+			       unsigned long baudrate, bool use_dte)
+{
+	u32 tmp;
+
+	tmp = RFDIV << UFCR_RFDIV_SHF;
+	if (use_dte)
+		tmp |= UFCR_DCEDTE;
+	else
+		tmp |= (TXTL << UFCR_TXTL_SHF) | (RXTL << UFCR_RXTL_SHF);
+	writel(tmp, &base->fcr);
+
+	writel(0xf, &base->bir);
+	writel(clk / (2 * baudrate), &base->bmr);
+
+	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
+	       &base->cr2);
+	writel(UCR1_UARTEN, &base->cr1);
+}
+
 #ifndef CONFIG_DM_SERIAL
 
 #ifndef CONFIG_MXC_UART_BASE
@@ -160,9 +182,6 @@ static void _mxc_serial_init(struct mxc_uart *base)
 
 #define mxc_base	((struct mxc_uart *)CONFIG_MXC_UART_BASE)
 
-#define TXTL  2 /* reset default */
-#define RXTL  1 /* reset default */
-
 static void mxc_serial_setbrg(void)
 {
 	u32 clk = imx_get_uartclk();
@@ -170,16 +189,7 @@ static void mxc_serial_setbrg(void)
 	if (!gd->baudrate)
 		gd->baudrate = CONFIG_BAUDRATE;
 
-	writel(((RFDIV << UFCR_RFDIV_SHF) |
-		(TXTL << UFCR_TXTL_SHF) |
-		(RXTL << UFCR_RXTL_SHF)),
-		&mxc_base->fcr);
-	writel(0xf, &mxc_base->bir);
-	writel(clk / (2 * gd->baudrate), &mxc_base->bmr);
-
-	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
-	       &mxc_base->cr2);
-	writel(UCR1_UARTEN, &mxc_base->cr1);
+	_mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);
 }
 
 static int mxc_serial_getc(void)
@@ -254,21 +264,9 @@ __weak struct serial_device *default_serial_console(void)
 int mxc_serial_setbrg(struct udevice *dev, int baudrate)
 {
 	struct mxc_serial_platdata *plat = dev->platdata;
-	struct mxc_uart *const uart = plat->reg;
 	u32 clk = imx_get_uartclk();
-	u32 tmp;
 
-	tmp = RFDIV << UFCR_RFDIV_SHF;
-	if (plat->use_dte)
-		tmp |= UFCR_DCEDTE;
-	writel(tmp, &uart->fcr);
-
-	writel(0xf, &uart->bir);
-	writel(clk / (2 * baudrate), &uart->bmr);
-
-	writel(UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST,
-	       &uart->cr2);
-	writel(UCR1_UARTEN, &uart->cr1);
+	_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);
 
 	return 0;
 }
-- 
1.9.1

[U-Boot] [PATCH 5/7] serial: mxc: Move common baud gen into _mxc_serial_setbrg

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Move the common baud generation code into _mxc_serial_setbrg
> so-that dm and non-dm can call this func.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 50 ++++++++++++++++++++++-----------------------
>  1 file changed, 24 insertions(+), 26 deletions(-)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 6/7] serial: mxc: Code cleanup

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

- Remove space between #define to macro
- Add tab between macro and value

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 drivers/serial/serial_mxc.c | 191 ++++++++++++++++++++++----------------------
 1 file changed, 94 insertions(+), 97 deletions(-)

diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 0fd3aaa..0bcd15c 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -15,99 +15,99 @@
 #include <linux/compiler.h>
 
 /* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  URXD_RX_DATA    (0xFF)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)	 /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)	 /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)	 /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)	 /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)	 /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)	 /* Send break */
-#define  UCR1_TDMAEN     (1<<3)	 /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)	 /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)	 /* Doze */
-#define  UCR1_UARTEN     (1<<0)	 /* UART enabled */
-#define  UCR2_ESCI	 (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS	 (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC	 (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8)  /* Parity enable */
-#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)	 /* Stop */
-#define  UCR2_WS         (1<<5)	 /* Word size */
-#define  UCR2_RTSEN      (1<<4)	 /* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)	 /* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)	 /* Receiver enabled */
-#define  UCR2_SRST	 (1<<0)	 /* SW reset */
-#define  UCR3_DTREN	 (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
-#define  UCR3_RXDSEN	 (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN	 (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25	 (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30	 (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT	 (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN	 (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR	 (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI	 (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN	 (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16	 (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC	 (1<<5)  /* IR special case */
-#define  UCR4_TCEN	 (1<<3)  /* Transmit complete interrupt enable */
-#define  UCR4_BKEN	 (1<<2)  /* Break condition interrupt enable */
-#define  UCR4_OREN	 (1<<1)  /* Receiver overrun interrupt enable */
-#define  UCR4_DREN	 (1<<0)  /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
-#define  UFCR_RFDIV_SHF  7      /* Reference freq divider shift */
-#define RFDIV		4 /* divide input clock by 2 */
-#define  UFCR_DCEDTE	 (1<<6)  /* DTE mode select */
-#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS	 (1<<14) /* RTS pin status */
-#define  USR1_TRDY	 (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD	 (1<<12) /* RTS delta */
-#define  USR1_ESCF	 (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)	 /* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)	 /* Receive timeout interrupt status */
-#define  USR1_RXDS	 (1<<6)	 /* Receiver idle interrupt flag */
-#define  USR1_AIRINT	 (1<<5)	 /* Async IR wake interrupt flag */
-#define  USR1_AWAKE	 (1<<4)	 /* Aysnc wake interrupt flag */
-#define  USR2_ADET	 (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE	 (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF	 (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE	 (1<<12) /* Idle condition */
-#define  USR2_IRINT	 (1<<8)	 /* Serial infrared interrupt flag */
-#define  USR2_WAKE	 (1<<7)	 /* Wake */
-#define  USR2_RTSF	 (1<<4)	 /* RTS edge interrupt flag */
-#define  USR2_TXDC	 (1<<3)	 /* Transmitter complete */
-#define  USR2_BRCD	 (1<<2)	 /* Break condition */
-#define  USR2_ORE        (1<<1)	 /* Overrun error */
-#define  USR2_RDR        (1<<0)	 /* Recv data ready */
-#define  UTS_FRCPERR	 (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY	 (1<<6)	 /* TxFIFO empty */
-#define  UTS_RXEMPTY	 (1<<5)	 /* RxFIFO empty */
-#define  UTS_TXFULL	 (1<<4)	 /* TxFIFO full */
-#define  UTS_RXFULL	 (1<<3)	 /* RxFIFO full */
-#define  UTS_SOFTRS	(1<<0)	 /* Software reset */
+#define URXD_CHARRDY	(1<<15)
+#define URXD_ERR	(1<<14)
+#define URXD_OVRRUN	(1<<13)
+#define URXD_FRMERR	(1<<12)
+#define URXD_BRK	(1<<11)
+#define URXD_PRERR	(1<<10)
+#define URXD_RX_DATA	(0xFF)
+#define UCR1_ADEN	(1<<15) /* Auto dectect interrupt */
+#define UCR1_ADBR	(1<<14) /* Auto detect baud rate */
+#define UCR1_TRDYEN	(1<<13) /* Transmitter ready interrupt enable */
+#define UCR1_IDEN	(1<<12) /* Idle condition interrupt */
+#define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
+#define UCR1_RDMAEN	(1<<8)	/* Recv ready DMA enable */
+#define UCR1_IREN	(1<<7)	/* Infrared interface enable */
+#define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
+#define UCR1_RTSDEN	(1<<5)	/* RTS delta interrupt enable */
+#define UCR1_SNDBRK	(1<<4)	/* Send break */
+#define UCR1_TDMAEN	(1<<3)	/* Transmitter ready DMA enable */
+#define UCR1_UARTCLKEN	(1<<2)	/* UART clock enabled */
+#define UCR1_DOZE	(1<<1)	/* Doze */
+#define UCR1_UARTEN	(1<<0)	/* UART enabled */
+#define UCR2_ESCI	(1<<15) /* Escape seq interrupt enable */
+#define UCR2_IRTS	(1<<14) /* Ignore RTS pin */
+#define UCR2_CTSC	(1<<13) /* CTS pin control */
+#define UCR2_CTS	(1<<12) /* Clear to send */
+#define UCR2_ESCEN	(1<<11) /* Escape enable */
+#define UCR2_PREN	(1<<8)  /* Parity enable */
+#define UCR2_PROE	(1<<7)  /* Parity odd/even */
+#define UCR2_STPB	(1<<6)	/* Stop */
+#define UCR2_WS		(1<<5)	/* Word size */
+#define UCR2_RTSEN	(1<<4)	/* Request to send interrupt enable */
+#define UCR2_TXEN	(1<<2)	/* Transmitter enabled */
+#define UCR2_RXEN	(1<<1)	/* Receiver enabled */
+#define UCR2_SRST	(1<<0)	/* SW reset */
+#define UCR3_DTREN	(1<<13) /* DTR interrupt enable */
+#define UCR3_PARERREN	(1<<12) /* Parity enable */
+#define UCR3_FRAERREN	(1<<11) /* Frame error interrupt enable */
+#define UCR3_DSR	(1<<10) /* Data set ready */
+#define UCR3_DCD	(1<<9)  /* Data carrier detect */
+#define UCR3_RI		(1<<8)  /* Ring indicator */
+#define UCR3_ADNIMP	(1<<7)  /* Autobaud Detection Not Improved */
+#define UCR3_RXDSEN	(1<<6)  /* Receive status interrupt enable */
+#define UCR3_AIRINTEN	(1<<5)  /* Async IR wake interrupt enable */
+#define UCR3_AWAKEN	(1<<4)  /* Async wake interrupt enable */
+#define UCR3_REF25	(1<<3)  /* Ref freq 25 MHz */
+#define UCR3_REF30	(1<<2)  /* Ref Freq 30 MHz */
+#define UCR3_INVT	(1<<1)  /* Inverted Infrared transmission */
+#define UCR3_BPEN	(1<<0)  /* Preset registers enable */
+#define UCR4_CTSTL_32	(32<<10) /* CTS trigger level (32 chars) */
+#define UCR4_INVR	(1<<9)  /* Inverted infrared reception */
+#define UCR4_ENIRI	(1<<8)  /* Serial infrared interrupt enable */
+#define UCR4_WKEN	(1<<7)  /* Wake interrupt enable */
+#define UCR4_REF16	(1<<6)  /* Ref freq 16 MHz */
+#define UCR4_IRSC	(1<<5)  /* IR special case */
+#define UCR4_TCEN	(1<<3)  /* Transmit complete interrupt enable */
+#define UCR4_BKEN	(1<<2)  /* Break condition interrupt enable */
+#define UCR4_OREN	(1<<1)  /* Receiver overrun interrupt enable */
+#define UCR4_DREN	(1<<0)  /* Recv data ready interrupt enable */
+#define UFCR_RXTL_SHF	0       /* Receiver trigger level shift */
+#define UFCR_RFDIV	(7<<7)  /* Reference freq divider mask */
+#define UFCR_RFDIV_SHF	7	/* Reference freq divider shift */
+#define RFDIV		4	/* divide input clock by 2 */
+#define UFCR_DCEDTE	(1<<6)  /* DTE mode select */
+#define UFCR_TXTL_SHF	10      /* Transmitter trigger level shift */
+#define USR1_PARITYERR	(1<<15) /* Parity error interrupt flag */
+#define USR1_RTSS	(1<<14) /* RTS pin status */
+#define USR1_TRDY	(1<<13) /* Transmitter ready interrupt/dma flag */
+#define USR1_RTSD	(1<<12) /* RTS delta */
+#define USR1_ESCF	(1<<11) /* Escape seq interrupt flag */
+#define USR1_FRAMERR	(1<<10) /* Frame error interrupt flag */
+#define USR1_RRDY	(1<<9)	/* Receiver ready interrupt/dma flag */
+#define USR1_TIMEOUT	(1<<7)	/* Receive timeout interrupt status */
+#define USR1_RXDS	(1<<6)	/* Receiver idle interrupt flag */
+#define USR1_AIRINT	(1<<5)	/* Async IR wake interrupt flag */
+#define USR1_AWAKE	(1<<4)	/* Aysnc wake interrupt flag */
+#define USR2_ADET	(1<<15) /* Auto baud rate detect complete */
+#define USR2_TXFE	(1<<14) /* Transmit buffer FIFO empty */
+#define USR2_DTRF	(1<<13) /* DTR edge interrupt flag */
+#define USR2_IDLE	(1<<12) /* Idle condition */
+#define USR2_IRINT	(1<<8)	/* Serial infrared interrupt flag */
+#define USR2_WAKE	(1<<7)	/* Wake */
+#define USR2_RTSF	(1<<4)	/* RTS edge interrupt flag */
+#define USR2_TXDC	(1<<3)	/* Transmitter complete */
+#define USR2_BRCD	(1<<2)	/* Break condition */
+#define USR2_ORE	(1<<1)	/* Overrun error */
+#define USR2_RDR	(1<<0)	/* Recv data ready */
+#define UTS_FRCPERR	(1<<13) /* Force parity error */
+#define UTS_LOOP	(1<<12) /* Loop tx and rx */
+#define UTS_TXEMPTY	(1<<6)	/* TxFIFO empty */
+#define UTS_RXEMPTY	(1<<5)	/* RxFIFO empty */
+#define UTS_TXFULL	(1<<4)	/* TxFIFO full */
+#define UTS_RXFULL	(1<<3)	/* RxFIFO full */
+#define UTS_SOFTRS	(1<<0)	/* Software reset */
 #define TXTL		2  /* reset default */
 #define RXTL		1  /* reset default */
 
@@ -212,9 +212,7 @@ static void mxc_serial_putc(const char c)
 		WATCHDOG_RESET();
 }
 
-/*
- * Test whether a character is in the RX buffer
- */
+/* Test whether a character is in the RX buffer */
 static int mxc_serial_tstc(void)
 {
 	/* If receive fifo is empty, return false */
@@ -226,7 +224,6 @@ static int mxc_serial_tstc(void)
 /*
  * Initialise the serial port with the given baudrate. The settings
  * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
  */
 static int mxc_serial_init(void)
 {
-- 
1.9.1

[U-Boot] [PATCH 6/7] serial: mxc: Code cleanup

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> - Remove space between #define to macro
> - Add tab between macro and value
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  drivers/serial/serial_mxc.c | 191 ++++++++++++++++++++++----------------------
>  1 file changed, 94 insertions(+), 97 deletions(-)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH 7/7] serial: mxc: Add debug uart support

[Jagan Teki]

From: Jagan Teki <jagan@amarulasolutions.com>

Add support for the debug UART to assist with early debugging.
Enable it for i.CoreM6 as an example.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
 configs/imx6qdl_icore_mmc_defconfig |  4 ++++
 drivers/serial/Kconfig              |  8 ++++++++
 drivers/serial/serial_mxc.c         | 26 ++++++++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig
index 4ab1fac..24010ec 100644
--- a/configs/imx6qdl_icore_mmc_defconfig
+++ b/configs/imx6qdl_icore_mmc_defconfig
@@ -44,3 +44,7 @@ CONFIG_IMX_THERMAL=y
 CONFIG_VIDEO_IPUV3=y
 CONFIG_PHYLIB=y
 CONFIG_PHY_SMSC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_MXC=y
+CONFIG_DEBUG_UART_BASE=0x021f0000
+CONFIG_DEBUG_UART_CLOCK=24000000
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 58fc7cd..32a3374 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -248,6 +248,14 @@ config DEBUG_UART_PIC32
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver model serial is running.
 
+config DEBUG_UART_MXC
+	bool "IMX Serial port"
+	depends on MXC_UART
+	help
+	  Select this to enable a debug UART using the serial_mxc driver. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver model serial is running.
+
 config DEBUG_UART_UNIPHIER
 	bool "UniPhier on-chip UART"
 	depends on ARCH_UNIPHIER
diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c
index 0bcd15c..18ff421 100644
--- a/drivers/serial/serial_mxc.c
+++ b/drivers/serial/serial_mxc.c
@@ -357,3 +357,29 @@ U_BOOT_DRIVER(serial_mxc) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 #endif
+
+#ifdef CONFIG_DEBUG_UART_MXC
+#include <debug_uart.h>
+
+static inline void _debug_uart_init(void)
+{
+	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+	_mxc_serial_init(base);
+	_mxc_serial_setbrg(base, CONFIG_DEBUG_UART_CLOCK,
+			   CONFIG_BAUDRATE, false);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	struct mxc_uart *base = (struct mxc_uart *)CONFIG_DEBUG_UART_BASE;
+
+	while (!(readl(&base->ts) & UTS_TXEMPTY))
+		WATCHDOG_RESET();
+
+	writel(ch, &base->txd);
+}
+
+DEBUG_UART_FUNCS
+
+#endif
-- 
1.9.1

[U-Boot] [PATCH 7/7] serial: mxc: Add debug uart support

[Simon Glass]

On 5 June 2017 at 23:31, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> From: Jagan Teki <jagan@amarulasolutions.com>
>
> Add support for the debug UART to assist with early debugging.
> Enable it for i.CoreM6 as an example.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
>  configs/imx6qdl_icore_mmc_defconfig |  4 ++++
>  drivers/serial/Kconfig              |  8 ++++++++
>  drivers/serial/serial_mxc.c         | 26 ++++++++++++++++++++++++++
>  3 files changed, 38 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>