From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL
Date: Tue, 6 Jun 2017 09:46:32 +0000 [thread overview]
Message-ID: <1496742391.2428.64.camel@intel.com> (raw)
In-Reply-To: <032b0da7-4818-f330-000a-85d6b9154375@denx.de>
On Sel, 2017-06-06 at 11:41 +0200, Marek Vasut wrote:
> On 06/06/2017 11:36 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-06-06 at 10:35 +0200, Marek Vasut wrote:
> > >
> > > On 06/06/2017 10:19 AM, Chee, Tien Fong wrote:
> > > >
> > > >
> > > > On Sel, 2017-06-06 at 10:03 +0200, Marek Vasut wrote:
> > > > >
> > > > >
> > > > > On 06/06/2017 08:35 AM, tien.fong.chee at intel.com wrote:
> > > > > >
> > > > > >
> > > > > >
> > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > >
> > > > > > This patch is for enabling FPGA driver support on SPL
> > > > > Why would we want that on Gen5 ? I believe this is only
> > > > > needed on
> > > > > Gen10.
> > > > >
> > > > I already moved the fpga_manager driver into drivers/fpga/ on
> > > > patch
> > > > 6,
> > > > and fpga_manager drivers are required on SPL. Actually
> > > > fpga_manager
> > > > driver should be part of the drivers/fpga.
> > > I think I miss some fundamental piece of information . Why would
> > > I
> > > need
> > > anything from the FPGA framework in SPL on Gen5 ? It is not
> > > needed
> > > thus
> > > far. Is it because you shuffled some of the code around or what ?
> > >
> > Because we need to know some status and mode type from FPGA even we
> > did
> > not program FPGA in SPL.
> But we didn't have this option enabled before and everything worked
> on
> gen5, why do we need it now ?
>
Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch 6.
next prev parent reply other threads:[~2017-06-06 9:46 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-06 6:35 [U-Boot] [PATCH v8 0/7] Add Intel Arria 10 SoC FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 1/7] arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 2/7] arm: socfpga: Restructure FPGA driver in the preparation to support A10 tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 3/7] arm: socfpga: Convert all Intel related FPGA configuration to Kconfig tien.fong.chee at intel.com
2017-06-06 7:57 ` Marek Vasut
2017-06-06 8:16 ` Chee, Tien Fong
2017-06-06 8:32 ` Marek Vasut
2017-06-06 8:48 ` Chee, Tien Fong
2017-06-06 8:53 ` Marek Vasut
2017-06-06 9:40 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:19 ` Chee, Tien Fong
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:36 ` Chee, Tien Fong
2017-06-06 9:41 ` Marek Vasut
2017-06-06 9:46 ` Chee, Tien Fong [this message]
2017-06-06 9:50 ` Marek Vasut
2017-06-07 3:06 ` Chee, Tien Fong
2017-06-07 6:36 ` Marek Vasut
2017-06-07 8:04 ` Chee, Tien Fong
2017-06-07 11:26 ` Chee, Tien Fong
2017-06-07 12:31 ` Marek Vasut
2017-06-08 3:40 ` Chee, Tien Fong
2017-06-08 12:14 ` Marek Vasut
2017-06-09 3:39 ` Chee, Tien Fong
2017-06-09 8:25 ` Marek Vasut
2017-06-09 13:52 ` Dinh Nguyen
2017-06-12 8:38 ` Chee, Tien Fong
2017-06-13 3:26 ` Chee, Tien Fong
2017-06-13 9:05 ` Marek Vasut
2017-06-14 5:35 ` Chee, Tien Fong
2017-06-19 10:32 ` Chee, Tien Fong
2017-06-19 13:18 ` Dinh Nguyen
2017-06-07 12:30 ` Marek Vasut
2017-06-06 6:35 ` [U-Boot] [PATCH v8 5/7] drivers: Enable FPGA driver build " tien.fong.chee at intel.com
2017-06-06 8:03 ` Marek Vasut
2017-06-06 8:26 ` Chee, Tien Fong
2017-06-06 8:35 ` Marek Vasut
2017-06-06 9:38 ` Chee, Tien Fong
2017-06-06 6:35 ` [U-Boot] [PATCH v8 6/7] arm: socfpga: Move FPGA manager driver to FPGA driver tien.fong.chee at intel.com
2017-06-06 6:35 ` [U-Boot] [PATCH v8 7/7] arm: socfpga: Add FPGA driver support for Arria 10 tien.fong.chee at intel.com
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