[U-Boot] [PATCH v8 4/7] arm: socfpga: Enable FPGA driver on SPL

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Kha, 2017-06-08 at 14:14 +0200, Marek Vasut wrote:
> On 06/08/2017 05:40 AM, Chee, Tien Fong wrote:
> [...]
> > 
> > > 
> > > > 
> > > > > 
> > > > > Any safety guideline?
> > > > > I checked the spl.map, we still have 10K left after
> > > > > calculation
> > > > > including bss size.
> > > > > 
> > > > I compiled all Intel fpga related defconfigs, and we have 9K
> > > > free
> > > > based
> > > > on total 64K memory size. SO building PFGA driver would
> > > > contribute
> > > > around 1~2K only to SPL size. Do you have concern with that?
> > > Yes
> > > 
> > > > 
> > > > 
> > > > If you have concern, i would remove patch 6, keep fpga_manager
> > > > intact.
> > > Can't you rework things such that they don't add useless code
> > > into
> > > the
> > > SPL instead ?
> > > 
> > I checked the codes yesterday, mostly are bridge, and HPS-FPGA
> > interface configuration in SPL. So, i think we can try to remove
> > them
> > as they are not required in SPL, but i need more time to test it
> > out
> > and ensure this change doesn't break anything.
> That's fine, we're past RC1 anyway.
> 
> > 
> > To avoid impact the progress of submitting the rest of patchset as
> > they
> > are still pending until this patchset is accepted , so i suggest we
> > can
> > do it in later. So, i will keep fpga_manager in there.
> > 
> > sounds good to you?
> You have about two months till the next MW opens , so if you want to
> flesh this out, please do.
> 
Sure, this changes will be in separate patchset, as this is for codes
cleaning up and refactoring on gen5.

So, how about the Add Arria 10 FPGA driver v10 patchset overall?
Anything else i miss?

Thanks.
> > 
> > > 
> > > > 
> > > > 
> > > > > 
> > > > > 
> > > > > Thanks.
>