From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Fri, 21 Jul 2017 05:33:20 +0000 Subject: [U-Boot] [PATCH v11 6/6] arm: socfpga: Add FPGA driver support for Arria 10 In-Reply-To: <4ae77b63-46de-f80e-43d6-af169b9d51d1@denx.de> References: <1499072829-5626-1-git-send-email-tien.fong.chee@intel.com> <1499072829-5626-8-git-send-email-tien.fong.chee@intel.com> <4ae77b63-46de-f80e-43d6-af169b9d51d1@denx.de> Message-ID: <1500615199.14844.1.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Rab, 2017-07-12 at 13:00 +0200, Marek Vasut wrote: > On 07/03/2017 11:07 AM, tien.fong.chee at intel.com wrote: > > > > From: Tien Fong Chee > > > > Add FPGA driver support for Arria 10. > > > > Signed-off-by: Tien Fong Chee > > Reviewed-by: Ley Foon Tan > > Reviewed-by: Dinh Nguyen > [...] > > > > > diff --git a/configs/socfpga_arria10_defconfig > > b/configs/socfpga_arria10_defconfig > > index 46bda47..53ab66f 100644 > > --- a/configs/socfpga_arria10_defconfig > > +++ b/configs/socfpga_arria10_defconfig > defconfig stuff should be in separate patch. > Okay. > > > > @@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10" > >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" > >  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" > >  CONFIG_SPL=y > > +CONFIG_SPL_FPGA_SUPPORT=y > >  CONFIG_CMD_BOOTZ=y > >  # CONFIG_CMD_IMLS is not set > >  CONFIG_CMD_ASKENV=y > > @@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y > >  # CONFIG_SPL_DOS_PARTITION is not set > >  CONFIG_SPL_DM=y > >  CONFIG_SPL_DM_SEQ_ALIAS=y > > +CONFIG_FPGA_SOCFPGA=y > >  CONFIG_DM_GPIO=y > >  CONFIG_DWAPB_GPIO=y > >  CONFIG_DM_MMC=y > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > index b65e5ba..08c9ff8 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o > >  obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o > >  obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o > >  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o > > +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o > >  endif > > diff --git a/drivers/fpga/socfpga_arria10.c > > b/drivers/fpga/socfpga_arria10.c > > new file mode 100644 > > index 0000000..5c717a8 > > --- /dev/null > > +++ b/drivers/fpga/socfpga_arria10.c > > @@ -0,0 +1,479 @@ > > +/* > > + * Copyright (C) 2017 Intel Corporation > > + * > > + * SPDX-License-Identifier:    GPL-2.0 > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +#define CFGWDTH_32 1 > > +#define MIN_BITSTREAM_SIZECHECK 230 > > +#define ENCRYPTION_OFFSET 69 > > +#define COMPRESSION_OFFSET 229 > > +#define FPGA_TIMEOUT_MSEC 1000  /* timeout in ms */ > > +#define FPGA_TIMEOUT_CNT 0x1000000 > > + > > +DECLARE_GLOBAL_DATA_PTR; > > + > > +static const struct socfpga_fpga_manager *fpga_manager_base = > > + (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; > > + > > +static const struct socfpga_system_manager *system_manager_base = > > + (void *)SOCFPGA_SYSMGR_ADDRESS; > > + > > +static void fpgamgr_set_cd_ratio(unsigned long ratio); > > + > > +static uint32_t fpgamgr_get_msel(void) > > +{ > > + u32 reg; > > + > > + reg = readl(&fpga_manager_base->imgcfg_stat); > > + reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >> > > + ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB; > > + > > + return reg; > > +} > > + > > +static void fpgamgr_set_cfgwdth(int width) > > +{ > > + if (width) > > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, > > + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK > > ); > > + else > > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, > > + ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK > > ); > > +} > > + > > +int is_fpgamgr_user_mode(void) > > +{ > > + return (readl(&fpga_manager_base->imgcfg_stat) & > > + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != > > 0; > > +} > > + > > +static int wait_for_user_mode(void) > > +{ > > + return wait_for_bit(__func__, > > + &fpga_manager_base->imgcfg_stat, > > + ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK, > > + 1, FPGA_TIMEOUT_MSEC, false); > > +} > > + > > +static int is_fpgamgr_early_user_mode(void) > > +{ > > + return (readl(&fpga_manager_base->imgcfg_stat) & > > + ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK > > ) != 0; > > +} > > + > > +int fpgamgr_wait_early_user_mode(void) > > +{ > > + u32 sync_data = 0xffffffff; > > + u32 i = 0; > > + unsigned start = get_timer(0); > > + unsigned long cd_ratio; > > + > > + /* Getting existing CDRATIO */ > > + cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) & > > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >> > > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB; > > + > > + /* Using CDRATIO_X1 for better compatibility */ > > + fpgamgr_set_cd_ratio(CDRATIO_x1); > > + > > + while (!(is_fpgamgr_early_user_mode())) { > The parens around is_fpga.... are superfluous, drop them. > Okay. > > > > + if (get_timer(start) > FPGA_TIMEOUT_MSEC) > > + return -ETIMEDOUT; > > + fpgamgr_program_write((const long unsigned int > > *)&sync_data, > > + sizeof(sync_data)); > > + udelay(FPGA_TIMEOUT_MSEC); > > + i++; > > + } > > + > > + debug("Additional %i sync word needed\n", i); > > + > > + /* restoring original CDRATIO */ > > + fpgamgr_set_cd_ratio(cd_ratio); > > + > > + return 0; > > +} > > + > > +/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de- > > asserted */ > > +static int wait_for_nconfig_pin_and_nstatus_pin(void) > > +{ > > + unsigned long mask = > > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK | > > + ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU > > S_PIN_SET_MSK; > > + > > + /* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop > > until de-asserted, > > +  * timeout at 1000ms > > +  */ > > + return wait_for_bit(__func__, > > +     &fpga_manager_base->imgcfg_stat, > > +     mask, > > +     false, FPGA_TIMEOUT_MSEC, false); > > +} > > + > > +static int wait_for_f2s_nstatus_pin(unsigned long value) > > +{ > > + /* Poll until f2s to specific value, timeout at 1000ms */ > > + return wait_for_bit(__func__, > > +     &fpga_manager_base->imgcfg_stat, > > +     ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PI > > N_SET_MSK, > > +     value, FPGA_TIMEOUT_MSEC, false); > > +} > > + > > +/* set CD ratio */ > > +static void fpgamgr_set_cd_ratio(unsigned long ratio) > > +{ > > + clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, > > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); > > + > > + setbits_le32(&fpga_manager_base->imgcfg_ctrl_02, > > + (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) & > > + ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK); > > +} > > + > > +/* get the MSEL value, verify we are set for FPP configuration > > mode */ > > +static int fpgamgr_verify_msel(void) > > +{ > > + u32 msel = fpgamgr_get_msel(); > > + > > + if ((msel != 0) && (msel != 1)) { > You mean if (msel & ~BIT(0)) ? > yes. > > > > + printf("Fail: read msel=%d\n", msel); > > + return -EPERM; > > + } > > + > > + return 0; > > +} > > + > > +/* > > + * Write cdratio and cdwidth based on whether the bitstream is > > compressed > > + * and/or encoded > > + */ > > +static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 > > *rbf_data, > > +        size_t rbf_size) > > +{ > > + unsigned int cd_ratio; > > + bool encrypt, compress; > > + > > + /* > > +         * According to the bitstream specification, > > +  * both encryption and compression status are > > +         * in location before offset 230 of the buffer. > > +         */ > > + if (rbf_size < MIN_BITSTREAM_SIZECHECK) > > + return -EINVAL; > > + > > + encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3; > > + encrypt = encrypt != 0; > > + > > + compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1; > > + compress = !compress; > > + > > + debug("header word %d = %08x\n", 69, rbf_data[69]); > > + debug("header word %d = %08x\n", 229, rbf_data[229]); > > + debug("read from rbf header: encrypt=%d compress=%d\n", > > encrypt, compress); > > + > > + /* > > +  * from the register map description of cdratio in > > imgcfg_ctrl_02: > > +  *  Normal Configuration    : 32bit Passive Parallel > > +  *  Partial Reconfiguration : 16bit Passive Parallel > > +  */ > > + > > + /* > > +  * cd ratio is dependent on cfg width and whether the > > bitstream > > +  * is encrypted and/or compressed. > > +  * > > +  * | width | encr. | compr. | cd ratio | > > +  * |  16   |   0   |   0    |     1    | > > +  * |  16   |   0   |   1    |     4    | > > +  * |  16   |   1   |   0    |     2    | > > +  * |  16   |   1   |   1    |     4    | > > +  * |  32   |   0   |   0    |     1    | > > +  * |  32   |   0   |   1    |     8    | > > +  * |  32   |   1   |   0    |     4    | > > +  * |  32   |   1   |   1    |     8    | > > +  */ > > + if (!compress && !encrypt) { > > + cd_ratio = CDRATIO_x1; > > + } else { > > + if (compress) > > + cd_ratio = CDRATIO_x4; > > + else > > + cd_ratio = CDRATIO_x2; > > + > > + /* if 32 bit, double the cd ratio (so register > > +    field setting is incremented) */ > > + if (cfg_width == CFGWDTH_32) > > + cd_ratio += 1; > > + } > > + > > + fpgamgr_set_cfgwdth(cfg_width); > > + fpgamgr_set_cd_ratio(cd_ratio); > > + > > + return 0; > > +} > [...] > > > > > diff --git a/include/configs/socfpga_common.h > > b/include/configs/socfpga_common.h > > index 1b79c03..edd973a 100644 > > --- a/include/configs/socfpga_common.h > > +++ b/include/configs/socfpga_common.h > > @@ -105,11 +105,10 @@ > >  /* > >   * FPGA Driver > >   */ > > -#ifdef CONFIG_TARGET_SOCFPGA_GEN5 > >  #ifdef CONFIG_CMD_FPGA > >  #define CONFIG_FPGA_COUNT 1 > >  #endif > > -#endif > Should be in separate patch, cf above. > okay. > > > >  /* > >   * L4 OSC1 Timer 0 > >   */ > > >