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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/5] arm: socfpga: Add checking function on searching boot device
Date: Wed, 2 Aug 2017 10:21:47 +0000	[thread overview]
Message-ID: <1501669306.4085.3.camel@intel.com> (raw)
In-Reply-To: <1d6c1492-03d9-111a-739f-7d6b237e2f53@denx.de>

On Isn, 2017-07-31 at 12:53 +0200, Marek Vasut wrote:
> On 07/31/2017 12:50 PM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Function for checking boot device type, which is required for
> > locating
> > flash where U-boot image, FPGA design are stored.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/include/mach/misc.h |   19
> > +++++++++++++++++++
> >  arch/arm/mach-socfpga/misc_arria10.c      |   22
> > ++++++++++++++++++++++
> >  2 files changed, 41 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
> > b/arch/arm/mach-socfpga/include/mach/misc.h
> > index 0b65783..b219aac 100644
> > --- a/arch/arm/mach-socfpga/include/mach/misc.h
> > +++ b/arch/arm/mach-socfpga/include/mach/misc.h
> > @@ -14,6 +14,24 @@ struct bsel {
> >  	const char	*name;
> >  };
> >  
> > +enum {
> > +	BOOT_DEVICE_RAM,
> > +	BOOT_DEVICE_MMC1,
> > +	BOOT_DEVICE_MMC2,
> > +	BOOT_DEVICE_MMC2_2,
> > +	BOOT_DEVICE_NAND,
> > +	BOOT_DEVICE_ONENAND,
> > +	BOOT_DEVICE_NOR,
> > +	BOOT_DEVICE_UART,
> > +	BOOT_DEVICE_SPI,
> > +	BOOT_DEVICE_USB,
> > +	BOOT_DEVICE_SATA,
> > +	BOOT_DEVICE_I2C,
> > +	BOOT_DEVICE_BOARD,
> > +	BOOT_DEVICE_DFU,
> > +	BOOT_DEVICE_NONE
> Why do you have so many bootdevices here if half of them aren't
> supported/used ?
> 
Okay, i will reduce it, i refered this from spl.h
> > 
> > +};
> > +
> >  extern struct bsel bsel_str[];
> >  
> >  #ifdef CONFIG_FPGA
> > @@ -26,6 +44,7 @@ static inline void socfpga_fpga_add(void) {}
> >  unsigned int dedicated_uart_com_port(const void *blob);
> >  unsigned int shared_uart_com_port(const void *blob);
> >  unsigned int uart_com_port(const void *blob);
> > +u32 boot_device(void);
> >  #endif
> >  
> >  #endif /* _MISC_H_ */
> > diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-
> > socfpga/misc_arria10.c
> > index 9d751f6..069a0a6 100644
> > --- a/arch/arm/mach-socfpga/misc_arria10.c
> > +++ b/arch/arm/mach-socfpga/misc_arria10.c
> > @@ -235,6 +235,28 @@ unsigned int uart_com_port(const void *blob)
> >  	return shared_uart_com_port(blob);
> >  }
> >  
> > +u32 boot_device(void)
> > +{
> > +	const u32 bsel = readl(&sysmgr_regs->bootinfo);
> > +
> > +	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
> This looks very similar to what is on Gen5 ?
> 
I refered from  function spl_boot_device in spl.c . I copied the
function here, because U-boot also need it.
> > 
> > +	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
> > +		return BOOT_DEVICE_RAM;
> > +	case 0x2:	/* NAND Flash (1.8V) */
> > +	case 0x3:	/* NAND Flash (3.0V) */
> > +		return BOOT_DEVICE_NAND;
> > +	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
> > +	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
> > +		return BOOT_DEVICE_MMC1;
> > +	case 0x6:	/* QSPI Flash (1.8V) */
> > +	case 0x7:	/* QSPI Flash (3.0V) */
> > +		return BOOT_DEVICE_SPI;
> > +	default:
> > +		printf("Invalid boot device (bsel=%08x)!\n",
> > bsel);
> > +		hang();
> > +	}
> > +}
> > +
> >  /*
> >   * Print CPU information
> >   */
> > 
> 

  reply	other threads:[~2017-08-02 10:21 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-31 10:50 [U-Boot] [PATCH 0/5] Add intermediate driver(cff driver) between flash & FPGA tien.fong.chee at intel.com
2017-07-31 10:50 ` [U-Boot] [PATCH 1/5] arm: socfpga: Add checking function on searching boot device tien.fong.chee at intel.com
2017-07-31 10:53   ` Marek Vasut
2017-08-02 10:21     ` Chee, Tien Fong [this message]
2017-08-02 21:32       ` Marek Vasut
2017-08-04  5:37         ` Chee, Tien Fong
2017-08-04 13:10           ` Marek Vasut
2017-08-07  3:52             ` Chee, Tien Fong
2017-07-31 10:50 ` [U-Boot] [PATCH 2/5] arm: socfpga: Add checking function on FPGA setting in FDT tien.fong.chee at intel.com
2017-07-31 10:50 ` [U-Boot] [PATCH 3/5] configs: socfpga: Add config for RBF loading from FAT fs tien.fong.chee at intel.com
2017-07-31 10:54   ` Marek Vasut
2017-08-02 10:23     ` Chee, Tien Fong
2017-08-07  7:18     ` Chee, Tien Fong
2017-08-07  7:21       ` Marek Vasut
2017-07-31 10:50 ` [U-Boot] [PATCH 4/5] arm: socfpga: Add intermediate driver between flash and FPGA manager tien.fong.chee at intel.com
2017-07-31 10:55   ` Marek Vasut
2017-08-07  8:16     ` Chee, Tien Fong
2017-08-07  8:19       ` Marek Vasut
2017-08-07  8:43         ` Chee, Tien Fong
2017-07-31 10:50 ` [U-Boot] [PATCH 5/5] arm: socfpga: Enable cff driver build tien.fong.chee at intel.com

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