* [U-Boot] [PATCH] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
@ 2017-08-06 10:51 Pau Pajuelo
2017-08-07 20:26 ` Ladislav Michl
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
0 siblings, 2 replies; 11+ messages in thread
From: Pau Pajuelo @ 2017-08-06 10:51 UTC (permalink / raw)
To: u-boot
Update igep00x0 code with the following features:
- Add board and revision detection for the boards:
- IGEP0020-RF
- IGEP0020-RC
- IGEP0030-RG
- IGEP0030-RE
- Merge IGEP0020 and IGEP0030 mux tables
- Add suport to use GPIO_126, GPIO_127 and GPIO_129
- board_name environment variable displays board and revision information
Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
---
This patch allows to use a single configuration (igep00x0_defconfig)
in order to boot multiple IGEP OMAP3 boards with the same binaries.
Boards tested are: igep0020-rc, igep0020-rf, igep0030-re and igep0030-rg.
This is done using some GPIOs that differs signal level between boards
and versions.
GPIO_129, used to detect versions, needs a proper power domain configuration
through TPS65950 VSIM regulator as omap3 pandora board implements into the
patch 7cad446b887b6764afe8a6706508236bbd4998d8.
Finally, MUX_IGEP0020 and MUX_IGEP0030 can be merged to MUX_DEFAULT,
because they share the same functionality.
board/isee/igep00x0/MAINTAINERS | 3 +-
board/isee/igep00x0/igep00x0.c | 128 ++++++++++++++++++++++++++++++++++-----
board/isee/igep00x0/igep00x0.h | 13 ++--
configs/igep0020_defconfig | 44 --------------
configs/igep0030_defconfig | 43 -------------
configs/igep00x0_defconfig | 36 +++++++++++
include/configs/omap3_igep00x0.h | 25 +++++---
7 files changed, 170 insertions(+), 122 deletions(-)
delete mode 100644 configs/igep0020_defconfig
delete mode 100644 configs/igep0030_defconfig
create mode 100644 configs/igep00x0_defconfig
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
index 720ef2a..d75d400 100644
--- a/board/isee/igep00x0/MAINTAINERS
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com>
S: Maintained
F: board/isee/igep00x0/
F: include/configs/omap3_igep00x0.h
-F: configs/igep0020_defconfig
-F: configs/igep0030_defconfig
+F: configs/igep00x0_defconfig
F: configs/igep0032_defconfig
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 843d35e..be4b59c 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -17,7 +17,6 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand.h>
@@ -29,6 +28,43 @@
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Routine: get_board_revision
+ * Description: GPIO_28 and GPIO_129 are used to read board and revision from
+ * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
+ * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
+ * this functionality is shared by USB HOST.
+ * Once USB reset is applied, U-boot configures these pins as input pullup to
+ * detect board and revision:
+ * IGEP0020-RF = 0b00
+ * IGEP0020-RC = 0b01
+ * IGEP0030-RG = 0b10
+ * IGEP0030-RE = 0b11
+ */
+static int get_board_revision(void)
+{
+ int revision;
+
+ gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
+ "igep0030_usb_transceiver_reset");
+ gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
+
+ gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
+ gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
+ revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
+ gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
+
+ gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
+ "igep00x0_revision_detection");
+ gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
+ revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
+ gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
+
+ gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
+
+ return revision;
+}
+
static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
@@ -69,10 +105,6 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
return 0;
}
@@ -249,13 +281,62 @@ int ft_board_setup(void *blob, bd_t *bd)
void set_fdt(void)
{
- switch (gd->bd->bi_arch_number) {
- case MACH_TYPE_IGEP0020:
+ switch (get_board_revision()) {
+ case 0:
+ setenv("fdtfile", "omap3-igep0020-rev-f.dtb");
+ break;
+ case 1:
setenv("fdtfile", "omap3-igep0020.dtb");
break;
- case MACH_TYPE_IGEP0030:
+ case 2:
+ setenv("fdtfile", "omap3-igep0030-rev-g.dtb");
+ break;
+ case 3:
setenv("fdtfile", "omap3-igep0030.dtb");
break;
+ default:
+ /* Should not happen... */
+ break;
+ }
+}
+
+void set_led(void)
+{
+ switch (get_board_revision()) {
+ case 0:
+ case 1:
+ gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
+ gpio_direction_output(IGEP0020_GPIO_LED, 1);
+ break;
+ case 2:
+ case 3:
+ gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
+ gpio_direction_output(IGEP0030_GPIO_LED, 0);
+ break;
+ default:
+ /* Should not happen... */
+ break;
+ }
+}
+
+void set_boardname(void)
+{
+ switch (get_board_revision()) {
+ case 0:
+ setenv("board_name", "igep0020-rf");
+ break;
+ case 1:
+ setenv("board_name", "igep0020-rc");
+ break;
+ case 2:
+ setenv("board_name", "igep0030-rg");
+ break;
+ case 3:
+ setenv("board_name", "igep0030-re");
+ break;
+ default:
+ /* Should not happen... */
+ break;
}
}
@@ -265,14 +346,37 @@ void set_fdt(void)
*/
int misc_init_r(void)
{
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ u32 pbias_lite;
+
twl4030_power_init();
+ /* set VSIM to 1.8V */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+ TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* set up dual-voltage GPIOs to 1.8V */
+ pbias_lite = readl(&t2_base->pbias_lite);
+ pbias_lite &= ~PBIASLITEVMODE1;
+ pbias_lite |= PBIASLITEPWRDNZ1;
+ writel(pbias_lite, &t2_base->pbias_lite);
+ if (get_cpu_family() == CPU_OMAP36XX)
+ writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+ OMAP34XX_CTRL_WKUP_CTRL);
+
setup_net_chip();
omap_die_id_display();
set_fdt();
+ set_led();
+
+ set_boardname();
+
return 0;
}
@@ -302,12 +406,4 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
void set_muxconf_regs(void)
{
MUX_DEFAULT();
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
- MUX_IGEP0020();
-#endif
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
- MUX_IGEP0030();
-#endif
}
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
index 5698efa..1cbe7c9 100644
--- a/board/isee/igep00x0/igep00x0.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -103,6 +103,8 @@
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
@@ -117,13 +119,10 @@
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
+ MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
#endif
-
-#define MUX_IGEP0020() \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
-
-#define MUX_IGEP0030() \
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
diff --git a/configs/igep0020_defconfig b/configs/igep0020_defconfig
deleted file mode 100644
index 8ca5a84..0000000
--- a/configs/igep0020_defconfig
+++ /dev/null
@@ -1,44 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=27
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_MTD_UBI_FASTMAP=y
-CONFIG_SYS_NS16550=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
deleted file mode 100644
index 8af6dd5..0000000
--- a/configs/igep0030_defconfig
+++ /dev/null
@@ -1,43 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=16
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_SYS_NS16550=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig
new file mode 100644
index 0000000..75f6019
--- /dev/null
+++ b/configs/igep00x0_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TARGET_OMAP3_IGEP00X0=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_BOOTDELAY=3
+CONFIG_SYS_CONSOLE_IS_IN_ENV=y
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_VERSION_VARIABLE=y
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SPL=y
+# CONFIG_SPL_EXT_SUPPORT is not set
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_ONENAND_SUPPORT=y
+CONFIG_SPL_OS_BOOT=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_UBI=y
+# CONFIG_CMD_UBIFS is not set
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_SYS_NS16550=y
+CONFIG_FAT_WRITE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index 39f1e54..fee95d6 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -14,7 +14,6 @@
#define CONFIG_NAND
#include <configs/ti_omap3_common.h>
-#include <asm/mach-types.h>
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
@@ -27,15 +26,21 @@
#define CONFIG_REVISION_TAG 1
-/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
- (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-#define RED_LED_GPIO 27
-#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#define RED_LED_GPIO 16
-#endif
-#endif
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
+
+/* TPS65950 */
+#define PBIASLITEVMODE1 (1 << 8)
+
+/* LED */
+#define IGEP0020_GPIO_LED 27
+#define IGEP0030_GPIO_LED 16
+
+/* Board and revision detection GPIOs */
+#define IGEP0030_USB_TRANSCEIVER_RESET 54
+#define GPIO_IGEP00X0_BOARD_DETECTION 28
+#define GPIO_IGEP00X0_REVISION_DETECTION 129
/* USB */
#define CONFIG_USB_MUSB_UDC 1
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
2017-08-06 10:51 [U-Boot] [PATCH] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Pau Pajuelo
@ 2017-08-07 20:26 ` Ladislav Michl
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
1 sibling, 0 replies; 11+ messages in thread
From: Ladislav Michl @ 2017-08-07 20:26 UTC (permalink / raw)
To: u-boot
Hello Pau,
On Sun, Aug 06, 2017 at 12:51:38PM +0200, Pau Pajuelo wrote:
> Update igep00x0 code with the following features:
> - Add board and revision detection for the boards:
> - IGEP0020-RF
> - IGEP0020-RC
> - IGEP0030-RG
> - IGEP0030-RE
(it would be great to see this page updated:
http://labs.isee.biz/index.php/IGEP_Technology_devices_revisions)
> - Merge IGEP0020 and IGEP0030 mux tables
> - Add suport to use GPIO_126, GPIO_127 and GPIO_129
> - board_name environment variable displays board and revision information
nice idea!
> Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
Reviewed-by: Ladislav Michl <ladis@linux-mips.org>
Btw, once here, it would be nice to detect also CPU family as OMAP3530
devices cannot boot with omap3-igep0020.dtb and patch bellow is needed
(unless there is a better solution, I'll provide patch):
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index c16d17efe38e..1cafae7d8468 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -10,7 +10,7 @@
*/
/dts-v1/;
-#include "omap36xx.dtsi"
+#include "omap34xx.dtsi"
/ {
memory at 80000000 {
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index cc09842ad21b..0fa4ad499bec 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -13,7 +13,7 @@
/ {
model = "IGEPv2 Rev. C (TI OMAP AM/DM37x)";
- compatible = "isee,omap3-igep0020", "ti,omap36xx", "ti,omap3";
+ compatible = "isee,omap3-igep0020", "ti,omap3430", "ti,omap3";
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 0/2] igep00x0: defconfig merge
2017-08-06 10:51 [U-Boot] [PATCH] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Pau Pajuelo
2017-08-07 20:26 ` Ladislav Michl
@ 2017-08-17 1:05 ` Ladislav Michl
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
` (2 more replies)
1 sibling, 3 replies; 11+ messages in thread
From: Ladislav Michl @ 2017-08-17 1:05 UTC (permalink / raw)
To: u-boot
Hi Pau,
code with your patch "igep00x0: merge igep0020 and igep0030 defconfigs to
igep00x0_defconfig" applied no longer fits to sram (and patch even does
not apply anymore), so here's an update:
- move spl related functions to separate file
- update defconfig merge patch to current git
- use board_rev as other boards do
- set fdtfile using script (do not hardcode it)
best regards,
ladis
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
@ 2017-08-17 1:06 ` Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
2017-08-26 20:46 ` [U-Boot] [U-Boot, " Tom Rini
2017-08-17 1:09 ` [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Ladislav Michl
2017-08-18 22:01 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Pau Pajuelo
2 siblings, 2 replies; 11+ messages in thread
From: Ladislav Michl @ 2017-08-17 1:06 UTC (permalink / raw)
To: u-boot
Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
by moving SPL related functions into separate file.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---
board/isee/igep00x0/Makefile | 6 +-
board/isee/igep00x0/common.c | 80 ++++++++++++++++++++++++++
board/isee/igep00x0/igep00x0.c | 128 -----------------------------------------
board/isee/igep00x0/spl.c | 64 +++++++++++++++++++++
4 files changed, 149 insertions(+), 129 deletions(-)
diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
index 68b151c3c5..74594da771 100644
--- a/board/isee/igep00x0/Makefile
+++ b/board/isee/igep00x0/Makefile
@@ -5,4 +5,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := igep00x0.o
+ifdef CONFIG_SPL_BUILD
+obj-y := spl.o common.o
+else
+obj-y := igep00x0.o common.o
+endif
diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
new file mode 100644
index 0000000000..b8f1c14f6a
--- /dev/null
+++ b/board/isee/igep00x0/common.c
@@ -0,0 +1,80 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/omap_mmc.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/nand.h>
+#include "igep00x0.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ * hardware. Many pins need to be moved from protect to primary
+ * mode.
+ */
+void set_muxconf_regs(void)
+{
+ MUX_DEFAULT();
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
+ MUX_IGEP0020();
+#endif
+
+#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
+ MUX_IGEP0030();
+#endif
+}
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+ int loops = 100;
+
+ /* find out flash memory type, assume NAND first */
+ gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+ gpmc_init();
+
+ /* Issue a RESET and then READID */
+ writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
+ writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
+ while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
+ != NAND_STATUS_READY) {
+ udelay(1);
+ if (--loops == 0) {
+ gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+ gpmc_init(); /* reinitialize for OneNAND */
+ break;
+ }
+ }
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
+ status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
+#endif
+
+ return 0;
+}
+
+#if defined(CONFIG_MMC)
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, -1, -1);
+}
+
+void board_mmc_power_init(void)
+{
+ twl4030_power_mmc_init(0);
+}
+#endif
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index a7a75601dd..74f9bab093 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -20,15 +20,12 @@
#include <asm/mach-types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
-#include <linux/mtd/nand.h>
#include <linux/mtd/onenand.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <fdt_support.h>
#include "igep00x0.h"
-DECLARE_GLOBAL_DATA_PTR;
-
static const struct ns16550_platdata igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
@@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
&igep_serial
};
-/*
- * Routine: board_init
- * Description: Early hardware init.
- */
-int board_init(void)
-{
- int loops = 100;
-
- /* find out flash memory type, assume NAND first */
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- gpmc_init();
-
- /* Issue a RESET and then READID */
- writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
- writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
- while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
- != NAND_STATUS_READY) {
- udelay(1);
- if (--loops == 0) {
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- gpmc_init(); /* reinitialize for OneNAND */
- break;
- }
- }
-
- /* boot param addr */
- gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
- return 0;
-}
-
-#ifdef CONFIG_SPL_BUILD
-/*
- * Routine: get_board_mem_timings
- * Description: If we use SPL then there is no x-loader nor config header
- * so we have to setup the DDR timings ourself on both banks.
- */
-void get_board_mem_timings(struct board_sdrc_timings *timings)
-{
- int mfr, id, err = identify_nand_chip(&mfr, &id);
-
- timings->mr = MICRON_V_MR_165;
- if (!err) {
- switch (mfr) {
- case NAND_MFR_HYNIX:
- timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
- timings->ctrla = HYNIX_V_ACTIMA_200;
- timings->ctrlb = HYNIX_V_ACTIMB_200;
- break;
- case NAND_MFR_MICRON:
- timings->mcfg = MICRON_V_MCFG_200(256 << 20);
- timings->ctrla = MICRON_V_ACTIMA_200;
- timings->ctrlb = MICRON_V_ACTIMB_200;
- break;
- default:
- /* Should not happen... */
- break;
- }
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
- } else {
- if (get_cpu_family() == CPU_OMAP34XX) {
- timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_165;
- timings->ctrlb = NUMONYX_V_ACTIMB_165;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- } else {
- timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
- timings->ctrla = NUMONYX_V_ACTIMA_200;
- timings->ctrlb = NUMONYX_V_ACTIMB_200;
- timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
- }
- gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
- }
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif
-#endif
-
int onenand_board_init(struct mtd_info *mtd)
{
if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
@@ -199,20 +104,6 @@ int board_eth_init(bd_t *bis)
static inline void setup_net_chip(void) {}
#endif
-#if defined(CONFIG_MMC)
-int board_mmc_init(bd_t *bis)
-{
- return omap_mmc_init(0, 0, 0, -1, -1);
-}
-#endif
-
-#if defined(CONFIG_MMC)
-void board_mmc_power_init(void)
-{
- twl4030_power_mmc_init(0);
-}
-#endif
-
#ifdef CONFIG_OF_BOARD_SETUP
static int ft_enable_by_compatible(void *blob, char *compat, int enable)
{
@@ -292,22 +183,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
*mtdparts = parts;
}
}
-
-/*
- * Routine: set_muxconf_regs
- * Description: Setting up the configuration Mux registers specific to the
- * hardware. Many pins need to be moved from protect to primary
- * mode.
- */
-void set_muxconf_regs(void)
-{
- MUX_DEFAULT();
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
- MUX_IGEP0020();
-#endif
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
- MUX_IGEP0030();
-#endif
-}
diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c
new file mode 100644
index 0000000000..eb705cbe88
--- /dev/null
+++ b/board/isee/igep00x0/spl.c
@@ -0,0 +1,64 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/nand.h>
+#include "igep00x0.h"
+
+/*
+ * Routine: get_board_mem_timings
+ * Description: If we use SPL then there is no x-loader nor config header
+ * so we have to setup the DDR timings ourself on both banks.
+ */
+void get_board_mem_timings(struct board_sdrc_timings *timings)
+{
+ int mfr, id, err = identify_nand_chip(&mfr, &id);
+
+ timings->mr = MICRON_V_MR_165;
+ if (!err) {
+ switch (mfr) {
+ case NAND_MFR_HYNIX:
+ timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
+ timings->ctrla = HYNIX_V_ACTIMA_200;
+ timings->ctrlb = HYNIX_V_ACTIMB_200;
+ break;
+ case NAND_MFR_MICRON:
+ timings->mcfg = MICRON_V_MCFG_200(256 << 20);
+ timings->ctrla = MICRON_V_ACTIMA_200;
+ timings->ctrlb = MICRON_V_ACTIMB_200;
+ break;
+ default:
+ /* Should not happen... */
+ break;
+ }
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
+ } else {
+ if (get_cpu_family() == CPU_OMAP34XX) {
+ timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_165;
+ timings->ctrlb = NUMONYX_V_ACTIMB_165;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
+ } else {
+ timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
+ timings->ctrla = NUMONYX_V_ACTIMA_200;
+ timings->ctrlb = NUMONYX_V_ACTIMB_200;
+ timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
+ }
+ gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
+ }
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ /* break into full u-boot on 'c' */
+ if (serial_tstc() && serial_getc() == 'c')
+ return 1;
+
+ return 0;
+}
+#endif
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
@ 2017-08-17 1:09 ` Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
2017-08-26 20:46 ` [U-Boot] [U-Boot, PATCHv2, " Tom Rini
2017-08-18 22:01 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Pau Pajuelo
2 siblings, 2 replies; 11+ messages in thread
From: Ladislav Michl @ 2017-08-17 1:09 UTC (permalink / raw)
To: u-boot
From: Pau Pajuelo <ppajuel@gmail.com>
Update igep00x0 code with the following features:
- Add board and revision detection for the boards:
- IGEP0020-RF
- IGEP0020-RC
- IGEP0030-RG
- IGEP0030-RE
- Merge IGEP0020 and IGEP0030 mux tables
- Add suport to use GPIO_126, GPIO_127 and GPIO_129
- board_name and board_rev environment variables display board and
revision informations
- Move dtb name selection from code to boot script
Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
---
Changes:
-v2: Move dtb name selection from code to boot script
Use board_rev to hold board revision
board/isee/igep00x0/MAINTAINERS | 3 +-
board/isee/igep00x0/common.c | 12 ---
board/isee/igep00x0/igep00x0.c | 90 ++++++++++++++++++++--
board/isee/igep00x0/igep00x0.h | 13 ++--
configs/igep0030_defconfig | 47 -----------
configs/{igep0020_defconfig => igep00x0_defconfig} | 8 --
include/configs/omap3_igep00x0.h | 45 ++++++++---
7 files changed, 124 insertions(+), 94 deletions(-)
diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
index 720ef2aa69..d75d400eed 100644
--- a/board/isee/igep00x0/MAINTAINERS
+++ b/board/isee/igep00x0/MAINTAINERS
@@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com>
S: Maintained
F: board/isee/igep00x0/
F: include/configs/omap3_igep00x0.h
-F: configs/igep0020_defconfig
-F: configs/igep0030_defconfig
+F: configs/igep00x0_defconfig
F: configs/igep0032_defconfig
diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
index b8f1c14f6a..e59516f612 100644
--- a/board/isee/igep00x0/common.c
+++ b/board/isee/igep00x0/common.c
@@ -22,14 +22,6 @@ DECLARE_GLOBAL_DATA_PTR;
void set_muxconf_regs(void)
{
MUX_DEFAULT();
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
- MUX_IGEP0020();
-#endif
-
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
- MUX_IGEP0030();
-#endif
}
/*
@@ -60,10 +52,6 @@ int board_init(void)
/* boot param addr */
gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
-#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
- status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
-#endif
-
return 0;
}
diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
index 74f9bab093..5c7f256711 100644
--- a/board/isee/igep00x0/igep00x0.c
+++ b/board/isee/igep00x0/igep00x0.c
@@ -17,7 +17,6 @@
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/mux.h>
#include <asm/arch/sys_proto.h>
-#include <asm/mach-types.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/onenand.h>
@@ -38,6 +37,43 @@ U_BOOT_DEVICE(igep_uart) = {
&igep_serial
};
+/*
+ * Routine: get_board_revision
+ * Description: GPIO_28 and GPIO_129 are used to read board and revision from
+ * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
+ * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
+ * this functionality is shared by USB HOST.
+ * Once USB reset is applied, U-boot configures these pins as input pullup to
+ * detect board and revision:
+ * IGEP0020-RF = 0b00
+ * IGEP0020-RC = 0b01
+ * IGEP0030-RG = 0b10
+ * IGEP0030-RE = 0b11
+ */
+static int get_board_revision(void)
+{
+ int revision;
+
+ gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
+ "igep0030_usb_transceiver_reset");
+ gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
+
+ gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
+ gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
+ revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
+ gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
+
+ gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
+ "igep00x0_revision_detection");
+ gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
+ revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
+ gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
+
+ gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
+
+ return revision;
+}
+
int onenand_board_init(struct mtd_info *mtd)
{
if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
@@ -138,31 +174,69 @@ int ft_board_setup(void *blob, bd_t *bd)
}
#endif
-void set_fdt(void)
+void set_led(void)
{
- switch (gd->bd->bi_arch_number) {
- case MACH_TYPE_IGEP0020:
- env_set("fdtfile", "omap3-igep0020.dtb");
+ switch (get_board_revision()) {
+ case 0:
+ case 1:
+ gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
+ gpio_direction_output(IGEP0020_GPIO_LED, 1);
break;
- case MACH_TYPE_IGEP0030:
- env_set("fdtfile", "omap3-igep0030.dtb");
+ case 2:
+ case 3:
+ gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
+ gpio_direction_output(IGEP0030_GPIO_LED, 0);
+ break;
+ default:
+ /* Should not happen... */
break;
}
}
+void set_boardname(void)
+{
+ char rev[5] = { 'F','C','G','E', };
+ int i = get_board_revision();
+
+ rev[i+1] = 0;
+ env_set("board_rev", rev + i);
+ env_set("board_name", i < 2 ? "igep0020" : "igep0030");
+}
+
/*
* Routine: misc_init_r
* Description: Configure board specific parts
*/
int misc_init_r(void)
{
+ t2_t *t2_base = (t2_t *)T2_BASE;
+ u32 pbias_lite;
+
twl4030_power_init();
+ /* set VSIM to 1.8V */
+ twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
+ TWL4030_PM_RECEIVER_VSIM_VSEL_18,
+ TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
+ TWL4030_PM_RECEIVER_DEV_GRP_P1);
+
+ /* set up dual-voltage GPIOs to 1.8V */
+ pbias_lite = readl(&t2_base->pbias_lite);
+ pbias_lite &= ~PBIASLITEVMODE1;
+ pbias_lite |= PBIASLITEPWRDNZ1;
+ writel(pbias_lite, &t2_base->pbias_lite);
+ if (get_cpu_family() == CPU_OMAP36XX)
+ writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
+ OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
+ OMAP34XX_CTRL_WKUP_CTRL);
+
setup_net_chip();
omap_die_id_display();
- set_fdt();
+ set_led();
+
+ set_boardname();
return 0;
}
diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
index 5698efab5d..1cbe7c94d9 100644
--- a/board/isee/igep00x0/igep00x0.h
+++ b/board/isee/igep00x0/igep00x0.h
@@ -103,6 +103,8 @@
MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
+ MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+ MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
@@ -117,13 +119,10 @@
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
+ MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
#endif
-
-#define MUX_IGEP0020() \
- MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
-
-#define MUX_IGEP0030() \
- MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
- MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
deleted file mode 100644
index abf83c2522..0000000000
--- a/configs/igep0030_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_TARGET_OMAP3_IGEP00X0=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
-CONFIG_ENV_IS_NOWHERE=y
-CONFIG_BOOTDELAY=3
-CONFIG_SYS_CONSOLE_IS_IN_ENV=y
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL=y
-# CONFIG_SPL_EXT_SUPPORT is not set
-CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_ONENAND_SUPPORT=y
-CONFIG_SPL_OS_BOOT=y
-# CONFIG_CMD_IMLS is not set
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-# CONFIG_CMD_FLASH is not set
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_NAND=y
-CONFIG_CMD_ONENAND=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_CMD_UBI=y
-# CONFIG_CMD_UBIFS is not set
-CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=16
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
-CONFIG_MMC_OMAP_HS=y
-CONFIG_NAND=y
-CONFIG_SYS_NS16550=y
-CONFIG_OMAP3_SPI=y
-CONFIG_FAT_WRITE=y
-CONFIG_OF_LIBFDT=y
-CONFIG_FDT_FIXUP_PARTITIONS=y
diff --git a/configs/igep0020_defconfig b/configs/igep00x0_defconfig
similarity index 80%
rename from configs/igep0020_defconfig
rename to configs/igep00x0_defconfig
index 600434a4bb..1cdc73d766 100644
--- a/configs/igep0020_defconfig
+++ b/configs/igep00x0_defconfig
@@ -3,7 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TARGET_OMAP3_IGEP00X0=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_OF_BOARD_SETUP=y
-CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
CONFIG_ENV_IS_NOWHERE=y
CONFIG_BOOTDELAY=3
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
@@ -31,13 +30,6 @@ CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_UBI=y
# CONFIG_CMD_UBIFS is not set
CONFIG_NET_RANDOM_ETHADDR=y
-CONFIG_LED_STATUS=y
-CONFIG_LED_STATUS_GPIO=y
-CONFIG_LED_STATUS0=y
-CONFIG_LED_STATUS_BIT=27
-CONFIG_LED_STATUS_STATE=2
-CONFIG_LED_STATUS_BOOT_ENABLE=y
-CONFIG_LED_STATUS_BOOT=0
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_MTD_UBI_FASTMAP=y
diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
index a029b54804..dc137dbd41 100644
--- a/include/configs/omap3_igep00x0.h
+++ b/include/configs/omap3_igep00x0.h
@@ -13,7 +13,6 @@
#define CONFIG_NR_DRAM_BANKS 2
#include <configs/ti_omap3_common.h>
-#include <asm/mach-types.h>
/*
* We are only ever GP parts and will utilize all of the "downloaded image"
@@ -26,15 +25,21 @@
#define CONFIG_REVISION_TAG 1
-/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
- (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
-#define RED_LED_GPIO 27
-#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
-#define RED_LED_GPIO 16
-#endif
-#endif
+/* GPIO banks */
+#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
+#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
+
+/* TPS65950 */
+#define PBIASLITEVMODE1 (1 << 8)
+
+/* LED */
+#define IGEP0020_GPIO_LED 27
+#define IGEP0030_GPIO_LED 16
+
+/* Board and revision detection GPIOs */
+#define IGEP0030_USB_TRANSCEIVER_RESET 54
+#define GPIO_IGEP00X0_BOARD_DETECTION 28
+#define GPIO_IGEP00X0_REVISION_DETECTION 129
/* USB */
#define CONFIG_USB_MUSB_UDC 1
@@ -67,9 +72,29 @@
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0)
+#define CONFIG_BOOTCOMMAND \
+ "run findfdt; " \
+ "run distro_bootcmd"
+
#include <config_distro_bootcmd.h>
+#define ENV_FINDFDT \
+ "findfdt="\
+ "if test ${board_name} = igep0020; then " \
+ "if test ${board_rev} = F; then " \
+ "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
+ "else " \
+ "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
+ "if test ${board_name} = igep0030; then " \
+ "if test ${board_rev} = G; then " \
+ "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
+ "else " \
+ "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
+ "if test ${fdtfile} = ''; then " \
+ "echo WARNING: Could not determine device tree to use; fi; \0"
+
#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_FINDFDT \
ENV_DEVICE_SETTINGS \
MEM_LAYOUT_SETTINGS \
BOOTENV
--
2.11.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 0/2] igep00x0: defconfig merge
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
2017-08-17 1:09 ` [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Ladislav Michl
@ 2017-08-18 22:01 ` Pau Pajuelo
2 siblings, 0 replies; 11+ messages in thread
From: Pau Pajuelo @ 2017-08-18 22:01 UTC (permalink / raw)
To: u-boot
Hi ladis,
2017-08-17 3:05 GMT+02:00 Ladislav Michl <ladis@linux-mips.org>:
> Hi Pau,
>
> code with your patch "igep00x0: merge igep0020 and igep0030 defconfigs to
> igep00x0_defconfig" applied no longer fits to sram (and patch even does
> not apply anymore), so here's an update:
> - move spl related functions to separate file
> - update defconfig merge patch to current git
> - use board_rev as other boards do
> - set fdtfile using script (do not hardcode it)
>
> best regards,
> ladis
Now it looks more clear too
Best regards
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
@ 2017-08-18 22:02 ` Pau Pajuelo
2017-08-24 13:13 ` Enric Balletbo Serra
2017-08-26 20:46 ` [U-Boot] [U-Boot, " Tom Rini
1 sibling, 1 reply; 11+ messages in thread
From: Pau Pajuelo @ 2017-08-18 22:02 UTC (permalink / raw)
To: u-boot
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-08-17 3:06 GMT+02:00 Ladislav Michl <ladis@linux-mips.org>:
> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
> by moving SPL related functions into separate file.
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> ---
> board/isee/igep00x0/Makefile | 6 +-
> board/isee/igep00x0/common.c | 80 ++++++++++++++++++++++++++
> board/isee/igep00x0/igep00x0.c | 128 -----------------------------------------
> board/isee/igep00x0/spl.c | 64 +++++++++++++++++++++
> 4 files changed, 149 insertions(+), 129 deletions(-)
>
> diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
> index 68b151c3c5..74594da771 100644
> --- a/board/isee/igep00x0/Makefile
> +++ b/board/isee/igep00x0/Makefile
> @@ -5,4 +5,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
>
> -obj-y := igep00x0.o
> +ifdef CONFIG_SPL_BUILD
> +obj-y := spl.o common.o
> +else
> +obj-y := igep00x0.o common.o
> +endif
> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
> new file mode 100644
> index 0000000000..b8f1c14f6a
> --- /dev/null
> +++ b/board/isee/igep00x0/common.c
> @@ -0,0 +1,80 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#include <common.h>
> +#include <twl4030.h>
> +#include <asm/io.h>
> +#include <asm/omap_mmc.h>
> +#include <asm/arch/mux.h>
> +#include <asm/arch/sys_proto.h>
> +#include <jffs2/load_kernel.h>
> +#include <linux/mtd/nand.h>
> +#include "igep00x0.h"
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/*
> + * Routine: set_muxconf_regs
> + * Description: Setting up the configuration Mux registers specific to the
> + * hardware. Many pins need to be moved from protect to primary
> + * mode.
> + */
> +void set_muxconf_regs(void)
> +{
> + MUX_DEFAULT();
> +
> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
> + MUX_IGEP0020();
> +#endif
> +
> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> + MUX_IGEP0030();
> +#endif
> +}
> +
> +/*
> + * Routine: board_init
> + * Description: Early hardware init.
> + */
> +int board_init(void)
> +{
> + int loops = 100;
> +
> + /* find out flash memory type, assume NAND first */
> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> + gpmc_init();
> +
> + /* Issue a RESET and then READID */
> + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
> + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
> + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
> + != NAND_STATUS_READY) {
> + udelay(1);
> + if (--loops == 0) {
> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> + gpmc_init(); /* reinitialize for OneNAND */
> + break;
> + }
> + }
> +
> + /* boot param addr */
> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> +
> +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
> + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
> +#endif
> +
> + return 0;
> +}
> +
> +#if defined(CONFIG_MMC)
> +int board_mmc_init(bd_t *bis)
> +{
> + return omap_mmc_init(0, 0, 0, -1, -1);
> +}
> +
> +void board_mmc_power_init(void)
> +{
> + twl4030_power_mmc_init(0);
> +}
> +#endif
> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
> index a7a75601dd..74f9bab093 100644
> --- a/board/isee/igep00x0/igep00x0.c
> +++ b/board/isee/igep00x0/igep00x0.c
> @@ -20,15 +20,12 @@
> #include <asm/mach-types.h>
> #include <linux/mtd/mtd.h>
> #include <linux/mtd/nand.h>
> -#include <linux/mtd/nand.h>
> #include <linux/mtd/onenand.h>
> #include <jffs2/load_kernel.h>
> #include <mtd_node.h>
> #include <fdt_support.h>
> #include "igep00x0.h"
>
> -DECLARE_GLOBAL_DATA_PTR;
> -
> static const struct ns16550_platdata igep_serial = {
> .base = OMAP34XX_UART3,
> .reg_shift = 2,
> @@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
> &igep_serial
> };
>
> -/*
> - * Routine: board_init
> - * Description: Early hardware init.
> - */
> -int board_init(void)
> -{
> - int loops = 100;
> -
> - /* find out flash memory type, assume NAND first */
> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> - gpmc_init();
> -
> - /* Issue a RESET and then READID */
> - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
> - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
> - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
> - != NAND_STATUS_READY) {
> - udelay(1);
> - if (--loops == 0) {
> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> - gpmc_init(); /* reinitialize for OneNAND */
> - break;
> - }
> - }
> -
> - /* boot param addr */
> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
> -
> -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
> - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
> -#endif
> -
> - return 0;
> -}
> -
> -#ifdef CONFIG_SPL_BUILD
> -/*
> - * Routine: get_board_mem_timings
> - * Description: If we use SPL then there is no x-loader nor config header
> - * so we have to setup the DDR timings ourself on both banks.
> - */
> -void get_board_mem_timings(struct board_sdrc_timings *timings)
> -{
> - int mfr, id, err = identify_nand_chip(&mfr, &id);
> -
> - timings->mr = MICRON_V_MR_165;
> - if (!err) {
> - switch (mfr) {
> - case NAND_MFR_HYNIX:
> - timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
> - timings->ctrla = HYNIX_V_ACTIMA_200;
> - timings->ctrlb = HYNIX_V_ACTIMB_200;
> - break;
> - case NAND_MFR_MICRON:
> - timings->mcfg = MICRON_V_MCFG_200(256 << 20);
> - timings->ctrla = MICRON_V_ACTIMA_200;
> - timings->ctrlb = MICRON_V_ACTIMB_200;
> - break;
> - default:
> - /* Should not happen... */
> - break;
> - }
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> - } else {
> - if (get_cpu_family() == CPU_OMAP34XX) {
> - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
> - timings->ctrla = NUMONYX_V_ACTIMA_165;
> - timings->ctrlb = NUMONYX_V_ACTIMB_165;
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> - } else {
> - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
> - timings->ctrla = NUMONYX_V_ACTIMA_200;
> - timings->ctrlb = NUMONYX_V_ACTIMB_200;
> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> - }
> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> - }
> -}
> -
> -#ifdef CONFIG_SPL_OS_BOOT
> -int spl_start_uboot(void)
> -{
> - /* break into full u-boot on 'c' */
> - if (serial_tstc() && serial_getc() == 'c')
> - return 1;
> -
> - return 0;
> -}
> -#endif
> -#endif
> -
> int onenand_board_init(struct mtd_info *mtd)
> {
> if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
> @@ -199,20 +104,6 @@ int board_eth_init(bd_t *bis)
> static inline void setup_net_chip(void) {}
> #endif
>
> -#if defined(CONFIG_MMC)
> -int board_mmc_init(bd_t *bis)
> -{
> - return omap_mmc_init(0, 0, 0, -1, -1);
> -}
> -#endif
> -
> -#if defined(CONFIG_MMC)
> -void board_mmc_power_init(void)
> -{
> - twl4030_power_mmc_init(0);
> -}
> -#endif
> -
> #ifdef CONFIG_OF_BOARD_SETUP
> static int ft_enable_by_compatible(void *blob, char *compat, int enable)
> {
> @@ -292,22 +183,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
> *mtdparts = parts;
> }
> }
> -
> -/*
> - * Routine: set_muxconf_regs
> - * Description: Setting up the configuration Mux registers specific to the
> - * hardware. Many pins need to be moved from protect to primary
> - * mode.
> - */
> -void set_muxconf_regs(void)
> -{
> - MUX_DEFAULT();
> -
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
> - MUX_IGEP0020();
> -#endif
> -
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> - MUX_IGEP0030();
> -#endif
> -}
> diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c
> new file mode 100644
> index 0000000000..eb705cbe88
> --- /dev/null
> +++ b/board/isee/igep00x0/spl.c
> @@ -0,0 +1,64 @@
> +/*
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +#include <asm/io.h>
> +#include <asm/arch/mem.h>
> +#include <asm/arch/sys_proto.h>
> +#include <jffs2/load_kernel.h>
> +#include <linux/mtd/nand.h>
> +#include "igep00x0.h"
> +
> +/*
> + * Routine: get_board_mem_timings
> + * Description: If we use SPL then there is no x-loader nor config header
> + * so we have to setup the DDR timings ourself on both banks.
> + */
> +void get_board_mem_timings(struct board_sdrc_timings *timings)
> +{
> + int mfr, id, err = identify_nand_chip(&mfr, &id);
> +
> + timings->mr = MICRON_V_MR_165;
> + if (!err) {
> + switch (mfr) {
> + case NAND_MFR_HYNIX:
> + timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
> + timings->ctrla = HYNIX_V_ACTIMA_200;
> + timings->ctrlb = HYNIX_V_ACTIMB_200;
> + break;
> + case NAND_MFR_MICRON:
> + timings->mcfg = MICRON_V_MCFG_200(256 << 20);
> + timings->ctrla = MICRON_V_ACTIMA_200;
> + timings->ctrlb = MICRON_V_ACTIMB_200;
> + break;
> + default:
> + /* Should not happen... */
> + break;
> + }
> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
> + } else {
> + if (get_cpu_family() == CPU_OMAP34XX) {
> + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
> + timings->ctrla = NUMONYX_V_ACTIMA_165;
> + timings->ctrlb = NUMONYX_V_ACTIMB_165;
> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
> + } else {
> + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
> + timings->ctrla = NUMONYX_V_ACTIMA_200;
> + timings->ctrlb = NUMONYX_V_ACTIMB_200;
> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
> + }
> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
> + }
> +}
> +
> +#ifdef CONFIG_SPL_OS_BOOT
> +int spl_start_uboot(void)
> +{
> + /* break into full u-boot on 'c' */
> + if (serial_tstc() && serial_getc() == 'c')
> + return 1;
> +
> + return 0;
> +}
> +#endif
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
2017-08-17 1:09 ` [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Ladislav Michl
@ 2017-08-18 22:02 ` Pau Pajuelo
2017-08-26 20:46 ` [U-Boot] [U-Boot, PATCHv2, " Tom Rini
1 sibling, 0 replies; 11+ messages in thread
From: Pau Pajuelo @ 2017-08-18 22:02 UTC (permalink / raw)
To: u-boot
Tested-by: Pau Pajuelo <ppajuel@gmail.com>
2017-08-17 3:09 GMT+02:00 Ladislav Michl <ladis@linux-mips.org>:
> From: Pau Pajuelo <ppajuel@gmail.com>
>
> Update igep00x0 code with the following features:
> - Add board and revision detection for the boards:
> - IGEP0020-RF
> - IGEP0020-RC
> - IGEP0030-RG
> - IGEP0030-RE
> - Merge IGEP0020 and IGEP0030 mux tables
> - Add suport to use GPIO_126, GPIO_127 and GPIO_129
> - board_name and board_rev environment variables display board and
> revision informations
> - Move dtb name selection from code to boot script
>
> Signed-off-by: Pau Pajuelo <ppajuel@gmail.com>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> ---
> Changes:
> -v2: Move dtb name selection from code to boot script
> Use board_rev to hold board revision
>
> board/isee/igep00x0/MAINTAINERS | 3 +-
> board/isee/igep00x0/common.c | 12 ---
> board/isee/igep00x0/igep00x0.c | 90 ++++++++++++++++++++--
> board/isee/igep00x0/igep00x0.h | 13 ++--
> configs/igep0030_defconfig | 47 -----------
> configs/{igep0020_defconfig => igep00x0_defconfig} | 8 --
> include/configs/omap3_igep00x0.h | 45 ++++++++---
> 7 files changed, 124 insertions(+), 94 deletions(-)
>
> diff --git a/board/isee/igep00x0/MAINTAINERS b/board/isee/igep00x0/MAINTAINERS
> index 720ef2aa69..d75d400eed 100644
> --- a/board/isee/igep00x0/MAINTAINERS
> +++ b/board/isee/igep00x0/MAINTAINERS
> @@ -3,6 +3,5 @@ M: Enric Balletbo i Serra <eballetbo@gmail.com>
> S: Maintained
> F: board/isee/igep00x0/
> F: include/configs/omap3_igep00x0.h
> -F: configs/igep0020_defconfig
> -F: configs/igep0030_defconfig
> +F: configs/igep00x0_defconfig
> F: configs/igep0032_defconfig
> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
> index b8f1c14f6a..e59516f612 100644
> --- a/board/isee/igep00x0/common.c
> +++ b/board/isee/igep00x0/common.c
> @@ -22,14 +22,6 @@ DECLARE_GLOBAL_DATA_PTR;
> void set_muxconf_regs(void)
> {
> MUX_DEFAULT();
> -
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
> - MUX_IGEP0020();
> -#endif
> -
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> - MUX_IGEP0030();
> -#endif
> }
>
> /*
> @@ -60,10 +52,6 @@ int board_init(void)
> /* boot param addr */
> gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>
> -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
> - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
> -#endif
> -
> return 0;
> }
>
> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
> index 74f9bab093..5c7f256711 100644
> --- a/board/isee/igep00x0/igep00x0.c
> +++ b/board/isee/igep00x0/igep00x0.c
> @@ -17,7 +17,6 @@
> #include <asm/arch/mmc_host_def.h>
> #include <asm/arch/mux.h>
> #include <asm/arch/sys_proto.h>
> -#include <asm/mach-types.h>
> #include <linux/mtd/mtd.h>
> #include <linux/mtd/nand.h>
> #include <linux/mtd/onenand.h>
> @@ -38,6 +37,43 @@ U_BOOT_DEVICE(igep_uart) = {
> &igep_serial
> };
>
> +/*
> + * Routine: get_board_revision
> + * Description: GPIO_28 and GPIO_129 are used to read board and revision from
> + * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from
> + * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because
> + * this functionality is shared by USB HOST.
> + * Once USB reset is applied, U-boot configures these pins as input pullup to
> + * detect board and revision:
> + * IGEP0020-RF = 0b00
> + * IGEP0020-RC = 0b01
> + * IGEP0030-RG = 0b10
> + * IGEP0030-RE = 0b11
> + */
> +static int get_board_revision(void)
> +{
> + int revision;
> +
> + gpio_request(IGEP0030_USB_TRANSCEIVER_RESET,
> + "igep0030_usb_transceiver_reset");
> + gpio_direction_output(IGEP0030_USB_TRANSCEIVER_RESET, 0);
> +
> + gpio_request(GPIO_IGEP00X0_BOARD_DETECTION, "igep00x0_board_detection");
> + gpio_direction_input(GPIO_IGEP00X0_BOARD_DETECTION);
> + revision = 2 * gpio_get_value(GPIO_IGEP00X0_BOARD_DETECTION);
> + gpio_free(GPIO_IGEP00X0_BOARD_DETECTION);
> +
> + gpio_request(GPIO_IGEP00X0_REVISION_DETECTION,
> + "igep00x0_revision_detection");
> + gpio_direction_input(GPIO_IGEP00X0_REVISION_DETECTION);
> + revision = revision + gpio_get_value(GPIO_IGEP00X0_REVISION_DETECTION);
> + gpio_free(GPIO_IGEP00X0_REVISION_DETECTION);
> +
> + gpio_free(IGEP0030_USB_TRANSCEIVER_RESET);
> +
> + return revision;
> +}
> +
> int onenand_board_init(struct mtd_info *mtd)
> {
> if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
> @@ -138,31 +174,69 @@ int ft_board_setup(void *blob, bd_t *bd)
> }
> #endif
>
> -void set_fdt(void)
> +void set_led(void)
> {
> - switch (gd->bd->bi_arch_number) {
> - case MACH_TYPE_IGEP0020:
> - env_set("fdtfile", "omap3-igep0020.dtb");
> + switch (get_board_revision()) {
> + case 0:
> + case 1:
> + gpio_request(IGEP0020_GPIO_LED, "igep0020_gpio_led");
> + gpio_direction_output(IGEP0020_GPIO_LED, 1);
> break;
> - case MACH_TYPE_IGEP0030:
> - env_set("fdtfile", "omap3-igep0030.dtb");
> + case 2:
> + case 3:
> + gpio_request(IGEP0030_GPIO_LED, "igep0030_gpio_led");
> + gpio_direction_output(IGEP0030_GPIO_LED, 0);
> + break;
> + default:
> + /* Should not happen... */
> break;
> }
> }
>
> +void set_boardname(void)
> +{
> + char rev[5] = { 'F','C','G','E', };
> + int i = get_board_revision();
> +
> + rev[i+1] = 0;
> + env_set("board_rev", rev + i);
> + env_set("board_name", i < 2 ? "igep0020" : "igep0030");
> +}
> +
> /*
> * Routine: misc_init_r
> * Description: Configure board specific parts
> */
> int misc_init_r(void)
> {
> + t2_t *t2_base = (t2_t *)T2_BASE;
> + u32 pbias_lite;
> +
> twl4030_power_init();
>
> + /* set VSIM to 1.8V */
> + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VSIM_DEDICATED,
> + TWL4030_PM_RECEIVER_VSIM_VSEL_18,
> + TWL4030_PM_RECEIVER_VSIM_DEV_GRP,
> + TWL4030_PM_RECEIVER_DEV_GRP_P1);
> +
> + /* set up dual-voltage GPIOs to 1.8V */
> + pbias_lite = readl(&t2_base->pbias_lite);
> + pbias_lite &= ~PBIASLITEVMODE1;
> + pbias_lite |= PBIASLITEPWRDNZ1;
> + writel(pbias_lite, &t2_base->pbias_lite);
> + if (get_cpu_family() == CPU_OMAP36XX)
> + writel(readl(OMAP34XX_CTRL_WKUP_CTRL) |
> + OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ,
> + OMAP34XX_CTRL_WKUP_CTRL);
> +
> setup_net_chip();
>
> omap_die_id_display();
>
> - set_fdt();
> + set_led();
> +
> + set_boardname();
>
> return 0;
> }
> diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h
> index 5698efab5d..1cbe7c94d9 100644
> --- a/board/isee/igep00x0/igep00x0.h
> +++ b/board/isee/igep00x0/igep00x0.h
> @@ -103,6 +103,8 @@
> MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /* MMC1_DAT1 */\
> MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /* MMC1_DAT2 */\
> MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /* MMC1_DAT3 */\
> + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
> + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */\
> MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /* UART3_TX */\
> MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /* UART3_RX */\
> MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) /* I2C1_SCL */\
> @@ -117,13 +119,10 @@
> MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /* GPIO_6 */\
> MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /* GPIO_7 */\
> MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /* GPIO_8 */\
> + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTU | EN | M4)) /* GPIO_28 */\
> + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTD | DIS | M4)) /* GPIO_54 */\
> + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64 */\
> + MUX_VAL(CP(GPIO129), (IEN | PTU | EN | M4)) /* GPIO_129 */\
> MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /* SDRC_CKE0 */\
> MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */
> #endif
> -
> -#define MUX_IGEP0020() \
> - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
> -
> -#define MUX_IGEP0030() \
> - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /* UART1_TX */\
> - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /* UART1_RX */
> diff --git a/configs/igep0030_defconfig b/configs/igep0030_defconfig
> deleted file mode 100644
> index abf83c2522..0000000000
> --- a/configs/igep0030_defconfig
> +++ /dev/null
> @@ -1,47 +0,0 @@
> -CONFIG_ARM=y
> -CONFIG_ARCH_OMAP2PLUS=y
> -CONFIG_TARGET_OMAP3_IGEP00X0=y
> -CONFIG_DISTRO_DEFAULTS=y
> -CONFIG_OF_BOARD_SETUP=y
> -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0030"
> -CONFIG_ENV_IS_NOWHERE=y
> -CONFIG_BOOTDELAY=3
> -CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> -CONFIG_SYS_CONSOLE_INFO_QUIET=y
> -CONFIG_VERSION_VARIABLE=y
> -# CONFIG_DISPLAY_BOARDINFO is not set
> -CONFIG_SPL=y
> -# CONFIG_SPL_EXT_SUPPORT is not set
> -CONFIG_SPL_MTD_SUPPORT=y
> -CONFIG_SPL_ONENAND_SUPPORT=y
> -CONFIG_SPL_OS_BOOT=y
> -# CONFIG_CMD_IMLS is not set
> -CONFIG_CMD_SPL=y
> -CONFIG_CMD_ASKENV=y
> -# CONFIG_CMD_FLASH is not set
> -CONFIG_CMD_GPIO=y
> -CONFIG_CMD_I2C=y
> -CONFIG_CMD_MMC=y
> -CONFIG_CMD_NAND=y
> -CONFIG_CMD_ONENAND=y
> -CONFIG_CMD_SPI=y
> -# CONFIG_CMD_SETEXPR is not set
> -CONFIG_CMD_CACHE=y
> -CONFIG_CMD_EXT4_WRITE=y
> -CONFIG_CMD_UBI=y
> -# CONFIG_CMD_UBIFS is not set
> -CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_LED_STATUS=y
> -CONFIG_LED_STATUS_GPIO=y
> -CONFIG_LED_STATUS0=y
> -CONFIG_LED_STATUS_BIT=16
> -CONFIG_LED_STATUS_STATE=2
> -CONFIG_LED_STATUS_BOOT_ENABLE=y
> -CONFIG_LED_STATUS_BOOT=0
> -CONFIG_MMC_OMAP_HS=y
> -CONFIG_NAND=y
> -CONFIG_SYS_NS16550=y
> -CONFIG_OMAP3_SPI=y
> -CONFIG_FAT_WRITE=y
> -CONFIG_OF_LIBFDT=y
> -CONFIG_FDT_FIXUP_PARTITIONS=y
> diff --git a/configs/igep0020_defconfig b/configs/igep00x0_defconfig
> similarity index 80%
> rename from configs/igep0020_defconfig
> rename to configs/igep00x0_defconfig
> index 600434a4bb..1cdc73d766 100644
> --- a/configs/igep0020_defconfig
> +++ b/configs/igep00x0_defconfig
> @@ -3,7 +3,6 @@ CONFIG_ARCH_OMAP2PLUS=y
> CONFIG_TARGET_OMAP3_IGEP00X0=y
> CONFIG_DISTRO_DEFAULTS=y
> CONFIG_OF_BOARD_SETUP=y
> -CONFIG_SYS_EXTRA_OPTIONS="MACH_TYPE=MACH_TYPE_IGEP0020"
> CONFIG_ENV_IS_NOWHERE=y
> CONFIG_BOOTDELAY=3
> CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> @@ -31,13 +30,6 @@ CONFIG_CMD_EXT4_WRITE=y
> CONFIG_CMD_UBI=y
> # CONFIG_CMD_UBIFS is not set
> CONFIG_NET_RANDOM_ETHADDR=y
> -CONFIG_LED_STATUS=y
> -CONFIG_LED_STATUS_GPIO=y
> -CONFIG_LED_STATUS0=y
> -CONFIG_LED_STATUS_BIT=27
> -CONFIG_LED_STATUS_STATE=2
> -CONFIG_LED_STATUS_BOOT_ENABLE=y
> -CONFIG_LED_STATUS_BOOT=0
> CONFIG_MMC_OMAP_HS=y
> CONFIG_NAND=y
> CONFIG_MTD_UBI_FASTMAP=y
> diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h
> index a029b54804..dc137dbd41 100644
> --- a/include/configs/omap3_igep00x0.h
> +++ b/include/configs/omap3_igep00x0.h
> @@ -13,7 +13,6 @@
> #define CONFIG_NR_DRAM_BANKS 2
>
> #include <configs/ti_omap3_common.h>
> -#include <asm/mach-types.h>
>
> /*
> * We are only ever GP parts and will utilize all of the "downloaded image"
> @@ -26,15 +25,21 @@
>
> #define CONFIG_REVISION_TAG 1
>
> -/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
> - (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
> -#define RED_LED_GPIO 27
> -#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
> -#define RED_LED_GPIO 16
> -#endif
> -#endif
> +/* GPIO banks */
> +#define CONFIG_OMAP3_GPIO_2 /* GPIO32..63 is in GPIO bank 2 */
> +#define CONFIG_OMAP3_GPIO_4 /* GPIO96..127 is in GPIO bank 4 */
> +
> +/* TPS65950 */
> +#define PBIASLITEVMODE1 (1 << 8)
> +
> +/* LED */
> +#define IGEP0020_GPIO_LED 27
> +#define IGEP0030_GPIO_LED 16
> +
> +/* Board and revision detection GPIOs */
> +#define IGEP0030_USB_TRANSCEIVER_RESET 54
> +#define GPIO_IGEP00X0_BOARD_DETECTION 28
> +#define GPIO_IGEP00X0_REVISION_DETECTION 129
>
> /* USB */
> #define CONFIG_USB_MUSB_UDC 1
> @@ -67,9 +72,29 @@
> #define BOOT_TARGET_DEVICES(func) \
> func(MMC, mmc, 0)
>
> +#define CONFIG_BOOTCOMMAND \
> + "run findfdt; " \
> + "run distro_bootcmd"
> +
> #include <config_distro_bootcmd.h>
>
> +#define ENV_FINDFDT \
> + "findfdt="\
> + "if test ${board_name} = igep0020; then " \
> + "if test ${board_rev} = F; then " \
> + "setenv fdtfile omap3-igep0020-rev-f.dtb; " \
> + "else " \
> + "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \
> + "if test ${board_name} = igep0030; then " \
> + "if test ${board_rev} = G; then " \
> + "setenv fdtfile omap3-igep0030-rev-g.dtb; " \
> + "else " \
> + "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \
> + "if test ${fdtfile} = ''; then " \
> + "echo WARNING: Could not determine device tree to use; fi; \0"
> +
> #define CONFIG_EXTRA_ENV_SETTINGS \
> + ENV_FINDFDT \
> ENV_DEVICE_SETTINGS \
> MEM_LAYOUT_SETTINGS \
> BOOTENV
> --
> 2.11.0
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file
2017-08-18 22:02 ` Pau Pajuelo
@ 2017-08-24 13:13 ` Enric Balletbo Serra
0 siblings, 0 replies; 11+ messages in thread
From: Enric Balletbo Serra @ 2017-08-24 13:13 UTC (permalink / raw)
To: u-boot
2017-08-19 0:02 GMT+02:00 Pau Pajuelo <ppajuel@gmail.com>:
> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
>
> 2017-08-17 3:06 GMT+02:00 Ladislav Michl <ladis@linux-mips.org>:
>> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
>> by moving SPL related functions into separate file.
>>
>> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
>> ---
>> board/isee/igep00x0/Makefile | 6 +-
>> board/isee/igep00x0/common.c | 80 ++++++++++++++++++++++++++
>> board/isee/igep00x0/igep00x0.c | 128 -----------------------------------------
>> board/isee/igep00x0/spl.c | 64 +++++++++++++++++++++
>> 4 files changed, 149 insertions(+), 129 deletions(-)
>>
>> diff --git a/board/isee/igep00x0/Makefile b/board/isee/igep00x0/Makefile
>> index 68b151c3c5..74594da771 100644
>> --- a/board/isee/igep00x0/Makefile
>> +++ b/board/isee/igep00x0/Makefile
>> @@ -5,4 +5,8 @@
>> # SPDX-License-Identifier: GPL-2.0+
>> #
>>
>> -obj-y := igep00x0.o
>> +ifdef CONFIG_SPL_BUILD
>> +obj-y := spl.o common.o
>> +else
>> +obj-y := igep00x0.o common.o
>> +endif
>> diff --git a/board/isee/igep00x0/common.c b/board/isee/igep00x0/common.c
>> new file mode 100644
>> index 0000000000..b8f1c14f6a
>> --- /dev/null
>> +++ b/board/isee/igep00x0/common.c
>> @@ -0,0 +1,80 @@
>> +/*
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#include <common.h>
>> +#include <twl4030.h>
>> +#include <asm/io.h>
>> +#include <asm/omap_mmc.h>
>> +#include <asm/arch/mux.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <jffs2/load_kernel.h>
>> +#include <linux/mtd/nand.h>
>> +#include "igep00x0.h"
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/*
>> + * Routine: set_muxconf_regs
>> + * Description: Setting up the configuration Mux registers specific to the
>> + * hardware. Many pins need to be moved from protect to primary
>> + * mode.
>> + */
>> +void set_muxconf_regs(void)
>> +{
>> + MUX_DEFAULT();
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
>> + MUX_IGEP0020();
>> +#endif
>> +
>> +#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
>> + MUX_IGEP0030();
>> +#endif
>> +}
>> +
>> +/*
>> + * Routine: board_init
>> + * Description: Early hardware init.
>> + */
>> +int board_init(void)
>> +{
>> + int loops = 100;
>> +
>> + /* find out flash memory type, assume NAND first */
>> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> + gpmc_init();
>> +
>> + /* Issue a RESET and then READID */
>> + writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
>> + writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
>> + while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> + != NAND_STATUS_READY) {
>> + udelay(1);
>> + if (--loops == 0) {
>> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> + gpmc_init(); /* reinitialize for OneNAND */
>> + break;
>> + }
>> + }
>> +
>> + /* boot param addr */
>> + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> +
>> +#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
>> + status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
>> +#endif
>> +
>> + return 0;
>> +}
>> +
>> +#if defined(CONFIG_MMC)
>> +int board_mmc_init(bd_t *bis)
>> +{
>> + return omap_mmc_init(0, 0, 0, -1, -1);
>> +}
>> +
>> +void board_mmc_power_init(void)
>> +{
>> + twl4030_power_mmc_init(0);
>> +}
>> +#endif
>> diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c
>> index a7a75601dd..74f9bab093 100644
>> --- a/board/isee/igep00x0/igep00x0.c
>> +++ b/board/isee/igep00x0/igep00x0.c
>> @@ -20,15 +20,12 @@
>> #include <asm/mach-types.h>
>> #include <linux/mtd/mtd.h>
>> #include <linux/mtd/nand.h>
>> -#include <linux/mtd/nand.h>
>> #include <linux/mtd/onenand.h>
>> #include <jffs2/load_kernel.h>
>> #include <mtd_node.h>
>> #include <fdt_support.h>
>> #include "igep00x0.h"
>>
>> -DECLARE_GLOBAL_DATA_PTR;
>> -
>> static const struct ns16550_platdata igep_serial = {
>> .base = OMAP34XX_UART3,
>> .reg_shift = 2,
>> @@ -41,98 +38,6 @@ U_BOOT_DEVICE(igep_uart) = {
>> &igep_serial
>> };
>>
>> -/*
>> - * Routine: board_init
>> - * Description: Early hardware init.
>> - */
>> -int board_init(void)
>> -{
>> - int loops = 100;
>> -
>> - /* find out flash memory type, assume NAND first */
>> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> - gpmc_init();
>> -
>> - /* Issue a RESET and then READID */
>> - writeb(NAND_CMD_RESET, &gpmc_cfg->cs[0].nand_cmd);
>> - writeb(NAND_CMD_STATUS, &gpmc_cfg->cs[0].nand_cmd);
>> - while ((readl(&gpmc_cfg->cs[0].nand_dat) & NAND_STATUS_READY)
>> - != NAND_STATUS_READY) {
>> - udelay(1);
>> - if (--loops == 0) {
>> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> - gpmc_init(); /* reinitialize for OneNAND */
>> - break;
>> - }
>> - }
>> -
>> - /* boot param addr */
>> - gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
>> -
>> -#if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
>> - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_ON);
>> -#endif
>> -
>> - return 0;
>> -}
>> -
>> -#ifdef CONFIG_SPL_BUILD
>> -/*
>> - * Routine: get_board_mem_timings
>> - * Description: If we use SPL then there is no x-loader nor config header
>> - * so we have to setup the DDR timings ourself on both banks.
>> - */
>> -void get_board_mem_timings(struct board_sdrc_timings *timings)
>> -{
>> - int mfr, id, err = identify_nand_chip(&mfr, &id);
>> -
>> - timings->mr = MICRON_V_MR_165;
>> - if (!err) {
>> - switch (mfr) {
>> - case NAND_MFR_HYNIX:
>> - timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
>> - timings->ctrla = HYNIX_V_ACTIMA_200;
>> - timings->ctrlb = HYNIX_V_ACTIMB_200;
>> - break;
>> - case NAND_MFR_MICRON:
>> - timings->mcfg = MICRON_V_MCFG_200(256 << 20);
>> - timings->ctrla = MICRON_V_ACTIMA_200;
>> - timings->ctrlb = MICRON_V_ACTIMB_200;
>> - break;
>> - default:
>> - /* Should not happen... */
>> - break;
>> - }
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> - gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> - } else {
>> - if (get_cpu_family() == CPU_OMAP34XX) {
>> - timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
>> - timings->ctrla = NUMONYX_V_ACTIMA_165;
>> - timings->ctrlb = NUMONYX_V_ACTIMB_165;
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> - } else {
>> - timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
>> - timings->ctrla = NUMONYX_V_ACTIMA_200;
>> - timings->ctrlb = NUMONYX_V_ACTIMB_200;
>> - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> - }
>> - gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> - }
>> -}
>> -
>> -#ifdef CONFIG_SPL_OS_BOOT
>> -int spl_start_uboot(void)
>> -{
>> - /* break into full u-boot on 'c' */
>> - if (serial_tstc() && serial_getc() == 'c')
>> - return 1;
>> -
>> - return 0;
>> -}
>> -#endif
>> -#endif
>> -
>> int onenand_board_init(struct mtd_info *mtd)
>> {
>> if (gpmc_cs0_flash == MTD_DEV_TYPE_ONENAND) {
>> @@ -199,20 +104,6 @@ int board_eth_init(bd_t *bis)
>> static inline void setup_net_chip(void) {}
>> #endif
>>
>> -#if defined(CONFIG_MMC)
>> -int board_mmc_init(bd_t *bis)
>> -{
>> - return omap_mmc_init(0, 0, 0, -1, -1);
>> -}
>> -#endif
>> -
>> -#if defined(CONFIG_MMC)
>> -void board_mmc_power_init(void)
>> -{
>> - twl4030_power_mmc_init(0);
>> -}
>> -#endif
>> -
>> #ifdef CONFIG_OF_BOARD_SETUP
>> static int ft_enable_by_compatible(void *blob, char *compat, int enable)
>> {
>> @@ -292,22 +183,3 @@ void board_mtdparts_default(const char **mtdids, const char **mtdparts)
>> *mtdparts = parts;
>> }
>> }
>> -
>> -/*
>> - * Routine: set_muxconf_regs
>> - * Description: Setting up the configuration Mux registers specific to the
>> - * hardware. Many pins need to be moved from protect to primary
>> - * mode.
>> - */
>> -void set_muxconf_regs(void)
>> -{
>> - MUX_DEFAULT();
>> -
>> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
>> - MUX_IGEP0020();
>> -#endif
>> -
>> -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
>> - MUX_IGEP0030();
>> -#endif
>> -}
>> diff --git a/board/isee/igep00x0/spl.c b/board/isee/igep00x0/spl.c
>> new file mode 100644
>> index 0000000000..eb705cbe88
>> --- /dev/null
>> +++ b/board/isee/igep00x0/spl.c
>> @@ -0,0 +1,64 @@
>> +/*
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +#include <asm/io.h>
>> +#include <asm/arch/mem.h>
>> +#include <asm/arch/sys_proto.h>
>> +#include <jffs2/load_kernel.h>
>> +#include <linux/mtd/nand.h>
>> +#include "igep00x0.h"
>> +
>> +/*
>> + * Routine: get_board_mem_timings
>> + * Description: If we use SPL then there is no x-loader nor config header
>> + * so we have to setup the DDR timings ourself on both banks.
>> + */
>> +void get_board_mem_timings(struct board_sdrc_timings *timings)
>> +{
>> + int mfr, id, err = identify_nand_chip(&mfr, &id);
>> +
>> + timings->mr = MICRON_V_MR_165;
>> + if (!err) {
>> + switch (mfr) {
>> + case NAND_MFR_HYNIX:
>> + timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
>> + timings->ctrla = HYNIX_V_ACTIMA_200;
>> + timings->ctrlb = HYNIX_V_ACTIMB_200;
>> + break;
>> + case NAND_MFR_MICRON:
>> + timings->mcfg = MICRON_V_MCFG_200(256 << 20);
>> + timings->ctrla = MICRON_V_ACTIMA_200;
>> + timings->ctrlb = MICRON_V_ACTIMB_200;
>> + break;
>> + default:
>> + /* Should not happen... */
>> + break;
>> + }
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> + gpmc_cs0_flash = MTD_DEV_TYPE_NAND;
>> + } else {
>> + if (get_cpu_family() == CPU_OMAP34XX) {
>> + timings->mcfg = NUMONYX_V_MCFG_165(256 << 20);
>> + timings->ctrla = NUMONYX_V_ACTIMA_165;
>> + timings->ctrlb = NUMONYX_V_ACTIMB_165;
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
>> + } else {
>> + timings->mcfg = NUMONYX_V_MCFG_200(256 << 20);
>> + timings->ctrla = NUMONYX_V_ACTIMA_200;
>> + timings->ctrlb = NUMONYX_V_ACTIMB_200;
>> + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
>> + }
>> + gpmc_cs0_flash = MTD_DEV_TYPE_ONENAND;
>> + }
>> +}
>> +
>> +#ifdef CONFIG_SPL_OS_BOOT
>> +int spl_start_uboot(void)
>> +{
>> + /* break into full u-boot on 'c' */
>> + if (serial_tstc() && serial_getc() == 'c')
>> + return 1;
>> +
>> + return 0;
>> +}
>> +#endif
>> --
>> 2.11.0
>>
Ladis, thanks for this patch.
Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [U-Boot, 1/2] igep00x0: move SPL routines into separate file
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
@ 2017-08-26 20:46 ` Tom Rini
1 sibling, 0 replies; 11+ messages in thread
From: Tom Rini @ 2017-08-26 20:46 UTC (permalink / raw)
To: u-boot
On Thu, Aug 17, 2017 at 03:06:45AM +0200, Ladislav Michl wrote:
> Avoid cluttering board file with CONFIG_SPL_BUILD ifdefs
> by moving SPL related functions into separate file.
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> Tested-by: Pau Pajuelo <ppajuel@gmail.com>
> Acked-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 11+ messages in thread
* [U-Boot] [U-Boot, PATCHv2, 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig
2017-08-17 1:09 ` [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
@ 2017-08-26 20:46 ` Tom Rini
1 sibling, 0 replies; 11+ messages in thread
From: Tom Rini @ 2017-08-26 20:46 UTC (permalink / raw)
To: u-boot
On Thu, Aug 17, 2017 at 03:09:14AM +0200, Ladislav Michl wrote:
> From: Pau Pajuelo <ppajuel@gmail.com>
>
> Update igep00x0 code with the following features:
Applied to u-boot/master, thanks!
--
Tom
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2017-08-26 20:46 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2017-08-06 10:51 [U-Boot] [PATCH] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Pau Pajuelo
2017-08-07 20:26 ` Ladislav Michl
2017-08-17 1:05 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Ladislav Michl
2017-08-17 1:06 ` [U-Boot] [PATCH 1/2] igep00x0: move SPL routines into separate file Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
2017-08-24 13:13 ` Enric Balletbo Serra
2017-08-26 20:46 ` [U-Boot] [U-Boot, " Tom Rini
2017-08-17 1:09 ` [U-Boot] [PATCHv2 2/2] igep00x0: merge igep0020 and igep0030 defconfigs to igep00x0_defconfig Ladislav Michl
2017-08-18 22:02 ` Pau Pajuelo
2017-08-26 20:46 ` [U-Boot] [U-Boot, PATCHv2, " Tom Rini
2017-08-18 22:01 ` [U-Boot] [PATCH 0/2] igep00x0: defconfig merge Pau Pajuelo
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