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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 4/5] arm: socfpga: Add intermediate driver between flash and FPGA manager
Date: Mon, 7 Aug 2017 08:16:06 +0000	[thread overview]
Message-ID: <1502093766.2357.26.camel@intel.com> (raw)
In-Reply-To: <927b9e08-0f9f-2d30-ab42-be60e5611074@denx.de>

On Isn, 2017-07-31 at 12:55 +0200, Marek Vasut wrote:
> On 07/31/2017 12:50 PM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Configuration flip-flop driver is mainly used for handling the FPGA
> > program
> > operation where the FPGA image loading from the flash into FPGA
> > manager.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  arch/arm/mach-socfpga/cff.c              |  581
> > ++++++++++++++++++++++++++++++
> >  arch/arm/mach-socfpga/include/mach/cff.h |   40 ++
> >  include/configs/socfpga_arria10_socdk.h  |    6 +
> >  3 files changed, 627 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-socfpga/cff.c
> >  create mode 100644 arch/arm/mach-socfpga/include/mach/cff.h
> > 
> Same comment as to previous patch, there is already support for
> loading
> FPGA from storage used by Xilinx, improve on that.
> 
Hi Marek,

After i going through the xilinx codes, i found that we are sharing
similar fpga framework design. The only different are the way of
decoding fpga design and loading from flash to fpga. So this would be
handled in cff.c, as for xilinx if i am not mistaken
is drivers/fpga/zynqpl.c. I think appropiate location for cff.c should
be in arch/mach-socfpga because this is not fpga driver, this is more
like platform specific algorithm mechanism to handle fpga decoding and
loading from flash to fpga. For the U-boot console command fpga loafs,
which will wrap the cff.c and acting as upper layer driver for  user
console interface. I plan to enhance this after having a complete boot
from sdmmc, qspi and nand because this require considering a lot use
case scenarios, and some workaround on PLL clock glitch issue. You know
our DDR IOs is part of the fpga periph rbf, simply calling fpga loadfs
to reconfigure fpga can corrupt the DDR IOs configuration, and board
may hang if it is not handle properly, so i need a workable complete
boot to console environment for testing out the enhancement.

Let me know what you think about this patchset, and can i continue
process with this patchset?

Thanks.

  reply	other threads:[~2017-08-07  8:16 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-07-31 10:50 [U-Boot] [PATCH 0/5] Add intermediate driver(cff driver) between flash & FPGA tien.fong.chee at intel.com
2017-07-31 10:50 ` [U-Boot] [PATCH 1/5] arm: socfpga: Add checking function on searching boot device tien.fong.chee at intel.com
2017-07-31 10:53   ` Marek Vasut
2017-08-02 10:21     ` Chee, Tien Fong
2017-08-02 21:32       ` Marek Vasut
2017-08-04  5:37         ` Chee, Tien Fong
2017-08-04 13:10           ` Marek Vasut
2017-08-07  3:52             ` Chee, Tien Fong
2017-07-31 10:50 ` [U-Boot] [PATCH 2/5] arm: socfpga: Add checking function on FPGA setting in FDT tien.fong.chee at intel.com
2017-07-31 10:50 ` [U-Boot] [PATCH 3/5] configs: socfpga: Add config for RBF loading from FAT fs tien.fong.chee at intel.com
2017-07-31 10:54   ` Marek Vasut
2017-08-02 10:23     ` Chee, Tien Fong
2017-08-07  7:18     ` Chee, Tien Fong
2017-08-07  7:21       ` Marek Vasut
2017-07-31 10:50 ` [U-Boot] [PATCH 4/5] arm: socfpga: Add intermediate driver between flash and FPGA manager tien.fong.chee at intel.com
2017-07-31 10:55   ` Marek Vasut
2017-08-07  8:16     ` Chee, Tien Fong [this message]
2017-08-07  8:19       ` Marek Vasut
2017-08-07  8:43         ` Chee, Tien Fong
2017-07-31 10:50 ` [U-Boot] [PATCH 5/5] arm: socfpga: Enable cff driver build tien.fong.chee at intel.com

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