From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 05/19] arm: socfpga: Enhance FPGA program support with at least 4 byte data
Date: Mon, 4 Sep 2017 07:09:05 +0000 [thread overview]
Message-ID: <1504508945.7727.74.camel@intel.com> (raw)
In-Reply-To: <556ddb8c-77ee-619d-3cc9-e70861395144@denx.de>
On Rab, 2017-08-30 at 10:55 +0200, Marek Vasut wrote:
> On 08/30/2017 10:24 AM, Chee, Tien Fong wrote:
> >
> > On Sel, 2017-08-29 at 13:58 +0200, Marek Vasut wrote:
> > >
> > > On 08/29/2017 12:45 PM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > This patch enables FPGA program with minimum 4 byte data size.
> > > What does that mean ? Expand the description, it's inobvious
> > >
> > The exisitng FPGA program function only support the FPGA data which
> > size is >= 32 bytes. For the size smaller than that, the operation
> > would have failed.
> Because ... ?
>
> And you fix it how ... ?
>
> That should be in the commit message, describe the problem and how
> you
> fix it.
>
Okay.
> >
> > >
> > > >
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > > drivers/fpga/socfpga.c | 14 ++++++++------
> > > > 1 files changed, 8 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/drivers/fpga/socfpga.c b/drivers/fpga/socfpga.c
> > > > index 28fa16b..6e14ebd 100644
> > > > --- a/drivers/fpga/socfpga.c
> > > > +++ b/drivers/fpga/socfpga.c
> > > > @@ -1,5 +1,5 @@
> > > > /*
> > > > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > > > + * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
> > > > * All rights reserved.
> > > > *
> > > > * SPDX-License-Identifier: BSD-3-Clause
> > > > @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void
> > > > *rbf_data, size_t rbf_size)
> > > > uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
> > > >
> > > > asm volatile(
> > > > + " cmp %2, #0\n"
> > > > + " beq 2f\n"
> > > > "1: ldmia %0!, {r0-r7}\n"
> > > > " stmia %1!, {r0-r7}\n"
> > > > " sub %1, #32\n"
> > > > " subs %2, #1\n"
> > > > " bne 1b\n"
> > > > - " cmp %3, #0\n"
> > > > - " beq 3f\n"
> > > > - "2: ldr %2, [%0],
> > > > #4\n
> > > > "
> > > > + "2: cmp %3, #0\n"
> > > > + " beq 4f\n"
> > > > + "3: ldr %2, [%0],
> > > > #4\n
> > > > "
> > > > " str %2, [%1]\n"
> > > > " subs %3, #1\n"
> > > > - " bne 2b\n"
> > > > - "3: nop\n"
> > > > + " bne 3b\n"
> > > > + "4: nop\n"
> > > > : "+r"(src), "+r"(dst), "+r"(loops32),
> > > > "+r"(loops4) :
> > > > : "r0", "r1", "r2", "r3", "r4", "r5", "r6",
> > > > "r7",
> > > > "cc");
> > > > }
> > > >
>
next prev parent reply other threads:[~2017-09-04 7:09 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-08-29 10:45 [U-Boot] [PATCH 00/19] Add FPGA, SDRAM drivers and booting to U-boot tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 01/19] configs: Add FPGA loadfs config for Arria 10 tien.fong.chee at intel.com
2017-08-29 11:51 ` Marek Vasut
2017-08-30 5:59 ` Chee, Tien Fong
2017-08-30 8:45 ` Marek Vasut
2017-09-04 5:29 ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 02/19] configs: Add FAT fs support for SPL tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA tien.fong.chee at intel.com
2017-08-29 11:55 ` Marek Vasut
2017-08-30 8:05 ` Chee, Tien Fong
2017-08-30 8:52 ` Marek Vasut
2017-09-04 7:08 ` Chee, Tien Fong
2017-09-04 9:39 ` Marek Vasut
2017-09-05 5:53 ` Chee, Tien Fong
2017-09-05 9:04 ` Marek Vasut
2017-09-05 9:23 ` Chee, Tien Fong
2017-09-05 9:36 ` Marek Vasut
2017-09-06 5:06 ` Chee, Tien Fong
2017-09-06 7:10 ` Marek Vasut
2017-09-06 7:15 ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 04/19] arm: socfpga: Add FPGA loadfs command support tien.fong.chee at intel.com
2017-08-29 11:57 ` Marek Vasut
2017-08-30 8:18 ` Chee, Tien Fong
2017-08-30 8:54 ` Marek Vasut
2017-08-29 10:45 ` [U-Boot] [PATCH 05/19] arm: socfpga: Enhance FPGA program support with at least 4 byte data tien.fong.chee at intel.com
2017-08-29 11:58 ` Marek Vasut
2017-08-30 8:24 ` Chee, Tien Fong
2017-08-30 8:55 ` Marek Vasut
2017-09-04 7:09 ` Chee, Tien Fong [this message]
2017-08-29 10:45 ` [U-Boot] [PATCH 06/19] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-08-29 11:59 ` Marek Vasut
2017-08-30 8:26 ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 07/19] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-08-29 11:59 ` Marek Vasut
2017-08-30 8:36 ` Chee, Tien Fong
2017-08-30 8:56 ` Marek Vasut
2017-09-04 7:11 ` Chee, Tien Fong
2017-09-04 9:40 ` Marek Vasut
2017-09-05 3:54 ` Chee, Tien Fong
2017-08-29 10:45 ` [U-Boot] [PATCH 08/19] arm: socfpga: Add COMPAT macro for Network on Chip(NoC) tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 09/19] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 10/19] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 11/19] arm: socfpga: Enable build for DDR " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 12/19] doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 13/19] dts: Add the FPGA design file name to DTS tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 14/19] dts: Add device storage and partition " tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 15/19] arm: socfpga: Add support to memory allocation in SPL tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-08-29 10:45 ` [U-Boot] [PATCH 17/19] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-08-29 10:46 ` [U-Boot] [PATCH 18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-08-29 10:46 ` [U-Boot] [PATCH 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot tien.fong.chee at intel.com
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